Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Bau Wu

Shun-Liang Hsu

Haw-Yun Wu

Chun Lin Tsai

Hsueh-Liang Chou

Ming-Cheng Lin

Weng-Chu Chu

Ruey-Hsin Liu

Tsung-Yi Huang

Fu-Jier Fan

Liang-Yu Su

Yun-Hsiang Wang

Chien-Shao Tang

Robin Hsieh

Kuo-Ming Wu

Yu-Chang Jong

You-Kuo Wu

Fang-Cheng Lui

Jiann-Tyng Tzeng

Jiun-Lei Jerry Yu

Kun-Ming Huang

Chun-Lin Tsai

Jyh-Min Jiang

Ruey-Hsin Liou

Kou-Chio Liu

A semiconductor device includes a first semiconductor structure including a first high electron mobility transistor (HEMT) device, wherein the first HEMT device includes a first gate, a first source, and a first drain; and a second semiconductor structure stacked above and bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second HEMT device and a third HEMT device, wherein the second HEMT device includes a second gate, a second source, and a second drain that is electrically connected to the first source, wherein the third HEMT device includes a third gate, a third source, and a third drain that is electrically connected to the first gate.

Wafer-on-wafer cascode HEMT device

In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer over a base substrate and an active layer over the channel layer. A source and a drain are over the active layer. A gate is over the active layer and laterally between the source and the drain. A dielectric is over the active layer and laterally surrounds the source, the drain, and the gate. A cap structure laterally contacts the source and is disposed laterally between the gate and the source. The source vertically extends to a top of the cap structure.

Cap structure coupled to source to reduce saturation current in HEMT device

In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer disposed over a base substrate, and an active layer disposed on the channel layer. A source contact and a drain contact are over the active layer and are laterally spaced apart from one another along a first direction. A gate electrode is arranged on the active layer between the source contact and the drain contact. A passivation layer is arranged on the active layer and laterally surrounds the source contact, the drain contact, and the gate electrode. A conductive structure is electrically coupled to the source contact and is disposed laterally between the gate electrode and the source contact. The conductive structure extends along an upper surface and a sidewall of the passivation layer.

In some embodiments, the present disclosure relates to a high voltage device that includes a substrate comprising a first semiconductor material. A channel layer that comprises a second semiconductor material is arranged over the substrate. An active layer that comprises a third semiconductor material is arranged over the channel layer. Over the active layer is a source contact spaced apart from a drain contact. A gate structure is arranged laterally between the source and drain contacts and over the active layer to define a high electron mobility transistor (HEMT) device. Between the gate structure and the source contact is a cap structure, which is coupled to the source contact and laterally spaced from the gate structure. The cap structure and a gate electrode of the gate structure comprise a same material.

The present disclosure relates to a semiconductor device including a first high electron mobility transistor (HEMT) device disposed within a semiconductor structure and having a first source, a first drain, and a first gate; a second HEMT device disposed within the semiconductor structure and having a second source, a second drain, and a second gate, the second source coupled to the first drain; and a diode-connected transistor device disposed within the semiconductor structure and comprising a third source, a third gate, and a third drain, the third drain coupled to the second gate.

High voltage cascode HEMT device

A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Coupling well structure for improving HVMOS performance

A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.

High voltage CMOS devices

A semiconductor structure includes a first high-voltage well (HVW) region of a first conductivity type overlying a substrate, a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region, and a third HVW region of the second conductivity type underlying the second HVW region. A region underlying the first HVW region is substantially free from the third HVW region, wherein the third HVW region has a bottom lower than a bottom of the first HVW region. The semiconductor structure further includes an insulation region in a portion and extending from a top surface of the first HVW region into the first HVW region, a gate dielectric extending from over the first HVW region to over the second HVW region wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Structures of high-voltage MOS devices with improved electrical performance

A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.

Semiconductor structure with high-voltage sustaining capability and fabrication method of the same

A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.

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Zhubei, Taiwan

Chen-Bau Wu