International Business Machines Corporation

Chekib Akrout

Pierre Coppens

Pierre-Yves Urena

Bernard A Denis

Yves Gautier

A reprogrammable logic fuse (RLF) based on a 6 device standard Static Random Access Memory (SRAM) cell includes a storage element comprised of four cross coupled FETs. A fifth FET is mounted in a transmission gate configuration between the bit line and a first common node of the storage element. Its gate electrode is connected to the word line. This FET is used to write the appropriate control data in the storage element for bit personality store. A sixth FET is also mounted in a transmission gate configuration between the second common node of the storage element and an output line. Its gate electrode is connected to the input line. This sixth FET ensures that a logical function, e.g. AND/NAND is achieved between the signals available at the second common node and on the input line. Other configurations of said sixth FET are allowed. These reprogrammable logic fuses may be disposed in matrixes to constitute reloadable logic arrays and Reloadable PLAs (RPLAs). In the latter case, in the AND array the input and output lines are respectively the product term lines (if bit partitioning is employed) and AND term lines (or Match Lines). In the OR array, the input and output lines are respectively the Match Out lines (the signal on the Match Line after complementation) and the OR out lines. RPLAs employing these RLF's can be dynamically reprogrammed to allow in system logical reconfiguration in real time.

Reprogrammable logic fuse based on a 6-device SRAM cell for logic arrays

In combination with an electronic memory of the type having a plurality of memory cells (CA, . . . CN) connected between two bit lines (BLT, BLC) having inherent bit line capacitances (C1, C2), there is disclosed an improved sense amplifier (15) comprised of two stages. A first stage (16) includes a first clocked latch (5) having an enable device (T5), gated by a first control signal (SSA) and bit switches (T6, T7) connected between the common nodes (6, 7) of said first clocked latch and said bit lines, and gated by a bit switch control signal (BS) to provide an output signal on first data lines (DLT, DLC). A second stage (17) includes a second clocked latch (20) having an enable device (T24) gated by a second signal (SL) and data switches (T28, T29) connected between second data lines (DT, DC) at the same potential as data output nodes (21, 22) of said second clocked latch and said first data lines (DLT, DLC). Said data switches (T28, T29) are gated by a data switch control signal (DS) which is derived from the bit switch control signal (BS), so that the first and second stages (16, 17) operate sequentially to amplify the data continuously along the sensing chain of the data path during a READ operation to provide a data output signal on said data output nodes. The data is then available for further processing at the output terminal (24) of the output driver (23).

Double stage sense amplifier for random access memories

A semiconductor memory device including a pair of bit lines (BL, BL) having relatively high stray capacitances (C1, C2), a word line (WL), and a memory cell (MC1) connected to the bit lines and word line for selection by an address signal, and a restore circuit comprising a coupling/equalizing circuit (12) controlled by a BLR clock and a reference voltage generator (51) for quickly restoring the bit lines. The reference voltage generator (51) comprises both static and dynamic current sources. The static current source consists of a small N MOS transistor (N52) operating as a resistor load, while the dynamic current source consists of at least one small P MOS transistor (P'53, . . . ), connected in parallel with the N MOS transistor, and gated with a clock (BCC', . . . ) derived from the BLR clock, so that the P MOS transistor is turned ON during the restore time. An additional N device (N54) may be inserted between the reference line (RL) and ground (GND). The improved reference voltage of the present invention significantly reduces both consumed silicon area and restore time.

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Ris Orangis, France

Chekib Akrout