Honeywell International Inc.

Honeywell G.m.b.h.

Other

Cheisan J Yue

Thomas R Keyser

Paul S Fechner

William Frank Witcraft

Eric E Vogt

Michael S Liu

James Douglas Seefeldt

Todd N Handeland

Todd A Randazzo

Hong Wan

William L Larson

Allan T Hurst, Jr

Curtis H Rahn

Gordon Alan Shaw

Mohammed A Fathimulla

Michael J Bohlinger

Bradley J Larsen

Tamara K Bratland

Tangshiun Yeh

Jeffrey Scott Sather

Jeffrey S Haviland

An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semiconductor substrate. The low resistivity guard ring is grounded and isolates the semiconductor mesa from RF signals.

Techniques to reduce substrate cross talk on mixed signal and RF circuit design

A neutron detection structure built from a Silicon-On-Insulator memory cell includes a conversion layer for converting incident neutrons into emitted charged particles, a device layer for receiving the emitted charged particles, a buried oxide layer separating the conversion layer from the device layer and directly adjacent to the conversion layer and the device layer, an isolation layer, a passivation layer formed on the isolation layer opposite the device layer and buried oxide layer, a carrier adhered by an adhesion layer to the passivation layer opposite the isolation layer, and a plurality of conductive contacts to provide electrical contact to the device layer. A corresponding method for fabricating such a structure includes permanently bonding a carrier to a passivated SOI SRAM wafer, removing an insulative substrate, depositing a conversion layer where at least a portion of the insulative substrate was removed, and forming at least one opening in the conversion layer and the buried oxide layer to provide at least one electrical contact to the device layer.

Neutron detection structure

The present invention provides silicon based thin-film structures that can be used to form high frequency optical modulators. Devices of the invention are formed as layered structures that have a thin-film dielectric layer, such as silicon dioxide, sandwiched between silicon layers. The silicon layers have high free carrier mobility. In one aspect of the invention a single crystal silicon material is bonded to a thin-film dielectric material to form a silicon-insulator-silicon thin-film structure for an optical modulator.

Bonded thin-film structures for optical modulators and methods of manufacture

At least one magnetic field sensing device and GPS receiver integrated in a discrete, single-chip package, and a method of manufacture for the same. Rather than requiring at least two separate chips to be used to realize GPS positioning and compassing capabilities in a single device, an integrated, single chip solution can be used. A single chip integration of a GPS receiver and at least one magnetic field sensing device can reduce the physical space required to provide positioning and electronic compassing capabilities in a single device, and therefore allow such devices to be smaller, lighter, and possibly more portable.

Method and apparatus for an integrated GPS receiver and electronic compassing sensor device

The present invention provides silicon based thin-film structures that can be used to form high frequency optical modulators. Devices of the invention are formed as layered structures that have a thin-film dielectric layer, such as silicon dioxide, sandwiched between silicon layers. The silicon layers have high free carrier mobility. In one aspect of the invention a high mobility silicon layer can be provided by crystallizing an amorphous silicon layer. In another aspect of the invention, a high mobility silicon layer can be provided by using selective epitaxial growth and extended lateral overgrowth thereof.

Silicon-insulator-silicon thin-film structures for optical modulators and methods of manufacture

A varactor has a plurality of alternating P&#x2212; wells and N+ regions formed in a silicon layer. Each of the P&#x2212; wells forms a first N+/P&#x2212; junction with the N+ region on one of its side and a second N+/P&#x2212; junction with the N+ region on the other of its sides. A gate oxide is provided over each of the P&#x2212; wells, and a gate silicon is provided over each of the gate oxides. The potential across the gate silicons and the N+ regions controls the capacitance of the varactor.

Varactor with improved tuning range

The present invention provides silicon based thin-film structures that can be used to form high frequency optical modulators. Devices of the invention are formed as layered structures that have a thin-film dielectric layer, such as silicon dioxide, sandwiched between silicon layers. In one aspect of the invention an electrical contact structure is provided. The electrical contact structure comprises a connecting portion that electrically connects an active region of at least one of the silicon layers to a contact portion of the electrical contact structure.

Low loss contact structures for silicon based optical modulators and methods of manufacture

A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of the second polysilicon area comprises contacts of the semiconductor device. Metal covers the polysilicon contacts.

Gate length control for semiconductor chip design

A method of forming a frontside contact to a Silicon-On-Insulator (SOI) wafer is described. A connection polysilicon connects a silicon substrate layer to a contact plug. This connection provides a means to ground or bias the bottom substrate of the SOI wafer. Spacers may be added to provide additional doping.

Frontside contact on silicon-on-insulator substrate

Formation of a frontside contact on silicon-on-insulator substrate

A process for oxidizing the silicon layer into a device-isolating field oxide having a radiation-hardened reduced bird's beak. An angled and rotated field implant prior to oxidation is used to increase the doping concentration in the edge region of the MOS transistors to compensate for boron leaching during oxidation. The field oxide is grown at a low temperature by high pressure oxidation which increases total dose hardness by making a silicon-rich oxide film.

Radiation hardened field oxide for VLSI sub-micron MOS device

A high density magnetic memory device and method of manufacture therefor, wherein the magnetic bit region is provided after selected higher temperature processing steps are performed. Illustrative higher temperature processing steps include those that are performed above for example 400.degree. C., any may include contact and via plug processing. The present invention may allow, for example, contact and via plug processing to be used to form magnetic RAM devices. As indicated above, contact and/or via plug processing typically allows the size of the contacts and vias to be reduced, and the packing density of the resulting memory device to be increased.

Method of manufacturing a high density magnetic memory device

A method for manufacturing magnetoresistive sensors whereby a first determination of an anisotropy field of the magnetoresistive material is made and an annealing temperature is selected based on a desired final value of the anisotropy field.

Growing community of inventors

Roseville, MN, United States of America

Cheisan J Yue