Industrial Technology Research Institute

United Microelectronics Corp.

National Science Council

Chein-Wei Jen

Chih-Wei Liu

Po-Han Huang

Tay-Jyi Lin

Chiao-Yen Tai

I-Tao Liao

Hwan-Rei Lee

Yung-Lung Chen

Li-Ren Huang

Gin-Kou Ma

Chan-Hao Chang

Wei-Sheng Huang

John-See Lee

Pi-Chen Hsiao

Chie-Min Chao

Chingson Chen

A method and corresponding apparatus for compiling high-level languages into specific processor architectures are provided. In this embodiment, the specific processor is encapsulated in a virtual processor interface with simple instruction set architecture, and a compiler translates application programs into corresponding assembly codes. Further, the difficulty of the compiler design is reduced.

Method and corresponding apparatus for compiling high-level languages into specific processor architectures

A two-piece wireless hearing improvement system having a pocket piece and an earpiece, wherein the pocket piece includes a microphone adapted to receive analog signals, a first processor coupled to the microphone to convert the analog signals to digital signals, and a first transceiver coupled to the processor to transmit the digital signals. The earpiece includes a second transceiver for receiving the digital signals, a second processor coupled to the second transceiver for converting the digital signals to analog signals, a speaker coupled to the second processor for transmitting the analog signals, and a movement detector for detecting relative movements between the earpiece and the pocket piece and generating a first signal according to the relative movements. The first processor provides signal compensation based on the first signal.

Wireless system and method thereof for hearing

A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer

An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

Inter-cluster communication module using the memory access network

Digital filter bank device that operates in a frequency-time hierarchically arranged, recursively fed back scheme based on the concept of decimation of a multi-speed-rate-operated system. The digital filter bank device operates in accordance with the computational requirement of summation of products for generating a filter output signal, and the computations are performed according to a software scheme based on a distributed arithmetic algorithm. The use of minimum hardware is enabled by a time-multiplexed scheme for both the implementation of the decimation and the distributed arithmetic principles of signal processing. The use of such a digital filter bank device results in a digital filter hardware architecture that has a significantly reduced semiconductor device die surface area.

Apparatus for filtering a signal utilizing recursion and decimation

Devices for computing discrete cosine transform, inverse discrete cosine transform or reduced ones, which require fewer transistors and less chip area, and which operate at a higher speed than those of the prior art. For example, the DCT/IDCT processor in the present invention essentially includes a matrix summation device and a plurality of shift adders. The matrix summation device computes a plurality of binary vectors from bits of an input vector, respectively for each term of an output vector. The shift-adding means respectively compute the terms of the output vector by sequentially left-shifting and adding the corresponding binary vectors.

Device for computing discrete cosine transform and inverse discrete

Apparatus and method of filtering a signal utilizing recursion and

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Hsinchu, Taiwan

Chein-Wei Jen