Sandisk Technologies Inc.

Sandisk Information Technology (shanghai) Co., Ltd.

Sandisk Semiconductor (shanghai) Co. Ltd.

Sandisk Corporation

Cheeman Yu

Hem P Takiar

Chin-Tien Chiu

Chih-Chin Liao

Ken Jian Ming Wang

Han-Shiao Chen

Zhong Lu

Jack Chang Chien

Chin Tien Chiu

Ning Liu

Wei Gu

Kaiyou Qian

Che-Jung Chang

Chi-Chin Liao

Peng Fu

Ya Huei Lee

Li Ping Wang

Ning Ye

Suresh Kumar Upadhyayula

Chien-Ko Liao

Vani Verma

Weili Wang

Fen Yu

Ye Bai

Kim Lee Bock

Weiting Jiang

Fuqiang Xiao

King Hoo Ong

Shiv Kumar

Gursharan Singh

Yuang Zhang

Enyong Tai

Didier Chavet

Pradeep Kumar Rai

Shan Luo

En-Yong Tai

Min Ni

Chin-Chin Liao

Matthew Chen

A system is disclosed for providing backward and forward traceability by a methodology which identifies discrete components (die, substrate and/or passives) that are included in a semiconductor device. The present technology further includes a system for generating a unique identifier and marking a semiconductor device with the unique identifier enabling the semiconductor device, and the discrete components within that device, to be tracked and traced through each process and test in the production of the semiconductor device.

Discrete component backward traceability and semiconductor device forward traceability

A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Printed circuit board with coextensive electrical connectors and contact pad areas

A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.

Semiconductor device including independent film layer for embedding and/or spacing semiconductor die

A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact.

Waterfall wire bonding

A memory device, and a method of making the memory device, are disclosed. The memory device is fabricated by mounting one or more semiconductor die on a substrate, and wire bonding the die to the substrate. The die and wire bonds are encapsuated, and the encapsulated device is singulated. The wire bonds are severed during the singulation step, and thereafter the severed wire bonds are connected to the substrate by external connectors on one or more surfaces of the molding compound.

Wire tail connector for a semiconductor device

A memory device including a metallic layer shielding electromagnetic radiation and/or dissipating heat, and a method of making the memory device, are disclosed. The metallic layer is formed on a metallic layer transfer assembly. The metallic layer transfer assembly and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the metallic layer is transferred from the shield to the encapsulated memory device.

EMI shielding and thermal dissipation for semiconductor device

A laminating device () and method are disclosed for laminating semiconductor die () on substrates on a panel () of substrates. The laminating device () includes lamination units () that operate independently of each other so that a row or column of semiconductor die () may be independently laminated onto a row or column of substrates simultaneously.

Semiconductor die laminating device with independent drives

A semiconductor device including two or more die stacks mounted to a substrate. The first die stack is mounted, at least partially encapsulated, and then tested. If the first die stack functions within predefined parameters, a second die stack is mounted on the first die stack, and then the device may undergo a second encapsulation process. Testing the first die stack before mounting the second improves yield by identifying faulty semiconductor die before all die are mounted within the semiconductor device.

High yield semiconductor device

A semiconductor device includes a substrate () with a cavity () formed therein for receiving a semiconductor die. In examples, the semiconductor die is a controller die (). The controller die () may be electrically connected to the substrate () with electrical traces () which may be formed for example by printing. After the controller die () is electrically connected to the substrate (), one or more memory die () may be affixed to the substrate (), over the cavity () and controller die ().

Semiconductor device including embedded controller die and method of making same

A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Hidden plating traces

A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package.

Semiconductor device with die stack arrangement including staggered die and efficient wire bonding

A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.

High density three dimensional semiconductor die package

A semiconductor die and semiconductor package formed therefrom, and methods of fabricating the semiconductor die and package, are disclosed. The semiconductor die includes an edge formed with a plurality of corrugations defined by protrusions between recesses. Bond pads may be formed on the protrusions. The semiconductor die formed in this manner may be stacked in the semiconductor package in staggered pairs so that the die bond pads on the protrusions of a lower die are positioned in the recesses of the upper die.

Corrugated die edge for stacked die semiconductor package

Growing community of inventors

Madison, WI, United States of America

Cheeman Yu