Intel Corporation

Chee-Yee Chung

David Gregory Figueroa

Yuan-Liang Li

Robert L Sankman

Alex Waizman

Bob Sankman

Farzaneh Yahyaei-moayyed

Kristopher J Frutschy

Hong Xie

James E Breisch

Kris Frutschy

Teong Guan Yew

Priyavadan R Patel

William Patrick Pinello

Chris Baldwin

Tee Onn Chong

A resistive element, a circuit board, and a circuit package, as well as a method of adding a resistive element to a circuit board are described. The resistive element includes a first contact point connected to a capacitor terminal, a second contact point connected to a circuit board plane, and resistive material connected to the first and second contact points. The invention may also include a circuit board with one or more resistive elements, as well as a circuit package, such as an integrated circuit or a discrete bypass capacitor, including one or more resistive elements, applied to an outside surface. The value of resistance for the resistive element can be selected by design to have a predetermined relationship with the equivalent resistance of an associated circuit board and connecting circuitry.

Resistive element apparatus and method

A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.

Capacitors having separate terminals on three or more sides

Arrangements are used to supply power to a semiconductor package.

Package stiffener

To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Integrated circuit packages with sandwiched capacitors

Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane. A method, according to one embodiment of the invention, includes the calculation of a first characteristic impedance of the dual referenced microstrip transmission line referenced to a primary reference layer, the calculation of a second characteristic impedance of the dual referenced microstrip transmission line referenced to a secondary reference layer, the calculation of an absolute value of a difference between the first and the second characteristic impedance, the comparison of the absolute value of the difference to a predetermined threshold value, and if the absolute value of the difference is greater than the predetermined threshold value, then a physical parameter associated with the characteristic impedance between the primary and secondary reference layers may be varied until the difference is reduced to less than the predetermined threshold. A structure, according to one embodiment of the invention includes a microstrip transmission line, a first conductive plane, a first dielectric layer provided between the microstrip transmission line and the first conductive plane, a second conductive plane, and a second dielectric layer provided between the first conductive plane and the second conductive plane.

Dual referenced microstrip

A power delivery system and a method for setting the parameters of the power delivery system. The effective resistance of the capacitors for each stage may be set to be substantially equal to the effective resistance of the previous stage, and the time capacitive constant of the capacitors may be set to be substantially equal to the effective inductive time constant of the previous stage.

Power delivery system having a plurality of stages and method for setting power delivery system parameters

Electronic assembly with sandwiched capacitors and methods of manufacture

A method for fabricating a socket (FIG.) includes fabricating a conductive structure (FIG.) and embedding the conductive structure in a housing (). The housing includes multiple openings () formed in the top surface. Each opening () provides access to conductive contacts (FIG.), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). In one embodiment, the embedded conductive structure () is electrically connected to one or more ground conducting contacts (FIG.B). The conductive structure includes column walls (), which run in parallel with columns of contacts, and row walls (), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (FIG.).

Method of fabrication for a socket with embedded conductive structure

An electronic circuit package includes a vertical package section ( , FIG. ) electrically connected to a horizontal package section ( , FIG. ). The vertical package section includes multiple conductive layers ( , FIG. ) oriented in parallel with a vertical plane. A first set of bond pads ( , FIG. ) on the vertical section's horizontal top surface ( , FIG. ) can be connected to the bond pads ( , FIG. ) of an integrated circuit ( , FIG. ). A second set of bond pads ( , FIG. ) on the vertical section's horizontal bottom surface ( , FIG. ) can be connected to bond pads ( , FIG. ) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures ( , FIG. ) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Electrical assembly with vertical multiple layer structure

Fabrication method for vertical electronic circuit package and system

An integrated circuit package and land side capacitor with reduced power delivery loop inductance. The capacitor pads have vias that lie underneath the land side capacitor, and have interposed digits.

Pad and via placement design for land side capacitors

An electronic assembly includes multiple discrete capacitors ( FIG. ), which are surface mounted to or embedded within an electronic housing, such as an integrated circuit package ( , FIG. ). One or more side terminals ( ) of adjacent capacitors are electrically connected through lateral connections ( , FIGS. ). These lateral connections provide an extremely low lateral inductance current path between the discrete capacitors.

Electronic assembly with laterally connected capacitors and manufacturing method

A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is slidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.

System and method for package socket with embedded power and ground planes

In one embodiment of the invention, an embedded enclosure includes a power plane and first and second ground planes. The power plane has a power surface and a power periphery, and couples power to signals of an integrated circuit operating at a fundamental frequency. The first and second ground planes have first and second ground surfaces and first and second ground peripheries, respectively. The first and second ground planes couple ground to the signals. The first and second ground planes are separated from the power plane by first and second distances, respectively. The first and second ground surfaces are larger than the power surface. The first and second ground peripheries extend at least third and fourth distances from the power periphery, respectively. The third and fourth distances are N and M times larger than the first and second distances, respectively.

Growing community of inventors

Chandler, AZ, United States of America

Chee-Yee Chung