Stmicroelectronics Asia Pacific Pte Limited

Stmicroelectronics Design and Application S.r.o.

Chee Weng Cheong

Dianbo Guo

Kien Beng Tan

Leonard Liviu Dinu

Yannick Guedon

Chaochao Zhang

Eng Jye Ng

Praveesh Chandran

Giuseppe Noviello

Baranidharan Karuppusamy

Kusuma Adi Ningrat

Hugo Gicquel

Teerasak Lee

Supriya Raveendra Hegde

Huiqiao He

Roman Prochazka

EngJye Ng

Chao Chao Zhang

Leonard Dinu

A wireless power receiver includes a rectifier with first and second inputs coupled to first and second terminals of a receiver coil, and having a first output coupled to ground and a second output at which a rectified voltage is produced. A first switch is coupled between the second input and ground, and is controlled by a first gate voltage generated at a first node. A second switch is coupled between the first node and ground, and is controlled by a second gate voltage. The first gate voltage closes the first switch to couple the second input to ground when the rectified voltage is less than a threshold voltage, boosting the rectified voltage. The second gate voltage closes the second switch to cause the second gate voltage to be pulled to ground when the rectified voltage is greater than the threshold voltage, limiting the boosting of the rectified voltage.

Adaptive boosting of rectified voltage in a wireless charging system

A wireless power receiving circuit includes a transistor based rectifier receiving an AC input voltage, and control logic receiving an overvoltage signal. The control logic generates control signals for controlling turn on of transistors within the transistor based rectifier based upon the overvoltage signal so as to cause the transistor based rectifier to produce a rectified output voltage from the AC input voltage. A comparator compares the rectified output voltage to a reference voltage and asserts the overvoltage signal if the rectified output voltage is greater than the reference voltage. In response to assertion of the overvoltage signal, the control logic asserts the control signals to simultaneously turn on all transistors of the transistor based rectifier.

Advanced overvoltage protection strategy for wireless power transfer

A system comprising includes a wireless power receiver generating a rectified voltage. A low dropout regulator (LDO) generates a first regulated output voltage from the rectified voltage, during a first phase. A first switch couples the first regulated output voltage to a voltage output node during the first phase. During a second phase, the LDO generates a second regulated output voltage from the rectified voltage. A switching regulator generates a third regulated output voltage during the second phase. A second switch couples the third regulated output voltage to the voltage output node during the second phase. During a third phase, the LDO is disabled, while the switching regulator continues to generate the third regulated output voltage. The first switch opens during the third phase while the second switch remains closed.

Dual-mode high-efficiency voltage regulator for wireless charging modules

A data demodulating circuit includes a sensing circuit sensing a power signal applied to a coil at first and second times, and outputting an analog value representing a difference in voltage of the power signal at the first and second times. An analog-to-digital converter digitizes the analog value output by the analog voltage differential sensing circuit to produce a digital code. A compensation circuit, over a period of time, compares a present value of the digital code to a first value of the digital code during the period, and subtracts a given value from the present value of the digital code if the present value is greater than the first value but add the given value to the present value of the digital code if the present value is less than the first value. An accumulator accumulates output of the compensation circuit, and a filter filters output of the accumulator.

Adaptive baseline correction for delta amplification

A capacitive discharge circuit includes a line having a capacitance, a switched capacitor circuit including a capacitor, a switched circuit coupled to the line, and a voltage regulator coupled between the switched capacitor circuit and the switched circuit. A controller operates the switched capacitor circuit and switched circuit to in a first phase, charge the capacitor by coupling the capacitor between a common mode and a power supply, and in a second phase, discharge the capacitor by coupling the voltage regulator in series with the capacitor between the power supply node a ground. The controller is also configured to in a third phase, charge the capacitor by coupling the capacitor between the common mode and the power supply, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator and the capacitor in series between the line and the ground.

Capacitive discharge circuit for touch sensitive screen

An electronic device disclosed herein includes a display layer generating display noise based on scanning thereof, and a sensing layer including a plurality of sense lines. A common voltage layer is coupled to the display layer and the sensing layer, with the common voltage layer capacitively coupling the display noise from the display layer to the each of the plurality of sense lines of the sensing layer via a different parasitic impedance. An amplitude of the display noise seen at an input to each sense line is a function of a location of that sense line. The electronic device includes a plurality of compensation impedances, with each compensation impedance coupled to a different one of the plurality of sense lines. Each of the plurality of compensation impedances has an impedance value such that an amplitude of the display noise at an output of each sense line is substantially equal.

Display noise compensation in touch screen display using capacitive dividers

A system and method for synchronizing two devices in communication with each other. When communication between the two devices is to be established, a synchronization process may be invoked. In an embodiment, a first device may initiate sending synchronization signals having rising edge and falling edge pairs. The second device may include a controller configured to receive the synchronization signals. However, noise may inhibit the ability of the controller to correctly receive and/or interpret the synchronization signals. Noise may cause detection components to falsely detect noise as a synchronization signal or may cause detection components to miss detection of an actual synchronization signal. A window generator may be used to generate comparison windows for the controller to detect synchronization signals. Further, the detection window duration and start times may be adjusted based on previously detected (or undetected) synchronization signals in order to compensate for noise overshadowing synchronization signals.

System and method for improved synchronization between devices

A circuit described herein includes a charge to voltage converter circuit having an input coupled to receive a sense signal from a sense node associated with a mutual capacitance to be sensed, and an output. A reset switch is coupled between the output of the charge to voltage converter circuit and the input of the charge to voltage converter. An accumulator circuit is configured to accumulate voltages at the output of the charge to voltage converter circuit and to generate an accumulator output signal. Control circuitry is configured to generate control signals for the reset switch and accumulator circuit so as to reduce noise in the accumulator output signal.

Sampling frequency and accumulator sweeping in a touch screen controller

An active stylus is capacitively coupled to a capacitive touch panel for communication. The active stylus operates in a wait mode to receive initial communications from the panel. In response to such receipt, the active stylus synchronizes to a repeating communications frame implementing time division multiplexing. Communications from the active stylus to the panel include: information communications; synchronization communications and communications specific for columns and/or rows of the panel. Communications from the panel to the active stylus may be addressed uniquely to the stylus or commonly to a group of styluses.

System and method of communication between a capacitive touch screen and an active stylus

A charge sensing circuit generates a voltage in a sensing period that is indicative of sensed charge. The generated voltages are accumulated by an accumulator circuit over a number of sensing periods. A noise detection circuit senses when the voltage generated by the charge sensing circuit is outside of a boundary and generates a detection signal in response thereto. A control circuit, in response to the detection signal, controls the accumulator circuit to block accumulation of the voltages generated by the charge sensing circuit during at least the sensing period in which the detection signal is generated. An analog-to-digital converter circuit then converts an accumulated output voltage from the accumulator circuit to a digital value at the end of an accumulation time period that includes the sensing periods. The end of the accumulation time period is delayed by at least one sensing period in response to the detection signal.

Method and apparatus for blocking accumulation of electrical fast transient (EFT) noise

A current mirror circuit includes an input current leg and an output current leg. The input current leg includes: a first bipolar junction transistor (BJT) having a collector terminal configured to receive an input current sourced at a current node and a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the first BJT. The output current leg includes: a second BJT having a collector terminal configured to supply an output current and a second MOSFET having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the second BJT.

Base current compensation for a BJT current mirror

A master-slave circuit is disclosed that maintains synchronization between two integrated circuit chips, using minimal chip resources. In one embodiment, a single, bidirectional communication path is shared by the two chips. Meanwhile, only one I/O port on each chip is used to send and receive signals via the bidirectional communication path. The first chip to detect a signal event is designated the master and controls the bidirectional communication path. The master can communicate the status to the other chip by controlling the logic state of the I/O ports. When the second chip detects that the I/O port is controlled by the first chip, the second chip will logically deduce that it is now the slave. If both chips detect the signal event at substantially the same time, one of the two chips is pre-programmed to assume control of the I/O port as the master.

Growing community of inventors

Singapore, Singapore

Chee Weng Cheong