National Taiwan University

Taiwan Semiconductor Manufacturing Comp. Ltd.

Atomic Energy Council

Chee Wee Liu

Chi-Wen Liu

Samuel C Pan

Pin-Shiang Chen

Hung-Yu Yeh

Sheng-Ting Fan

I-Hsieh Wong

Jhih-Yang Yan

Da-Zhi Zhang

Yen-Yu Chen

Yen-Ting Chen

Chien-Hua Huang

Hung-Chang Sun

Ching-Fang Huang

Chi-Fong Ai

Wen-Fa Tsai

Che-Yu Yeh

Bing J Sheu

Jyun-Jhe Tsai

Ying-Jhe Yang

Jyong-Fong Liao

Sun-Rong Jan

A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

Semiconductor device and method

A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.

Through silicon via layout pattern

Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.

Field effect transistors and methods of forming same

A method includes providing a substrate having a mesa, forming a first opening in the mesa, the first opening being surrounded by first inner sidewalls of the mesa exposed by the first opening. The method further includes etching from a first one of the first inner sidewalls of the mesa to form a first vertical recess, the first vertical recess having a wide end and a narrow end, with the narrow end defining a first vertically recessed channel region, and forming a first gate structure over the first vertically recessed channel region.

Three-dimensional transistor and methods of manufacturing thereof

Three-dimensional (3D) transistors and methods of manufacturing thereof include a first semiconductor fin extending over a substrate. The first semiconductor fin has a vertical recess extending from a first sidewall of the first semiconductor fin toward a second sidewall of the first semiconductor fin opposite the first sidewall. A distance between two opposing sidewalls of the vertical recess decreases as the vertical recess extends toward the second sidewall of the first semiconductor fin. The device further includes a vertically recessed channel region between the second sidewall of the first semiconductor fin and a bottom of the vertical recess, source/drain (S/D) regions at opposite ends of the vertically recessed channel region, and a gate stack over the vertically recessed channel region.

A structure and a method of the solar cell efficiency improvement by the strain technology are provided. The solar cell has a first surface and a second surfaces which at least a gasket is disposed thereon for supporting the solar cell and being the axle whiling stressing. The method includes the steps of: (a) applying at least a stress on the first surface; (b) generating a supporting force on the second surface; and (c) generating at least a strain in the solar cell. In addition, the present invention also includes a method involving a step of: (a) applying a mechanical stress to the solar cell; (b) generating a tension in the solar cell by at least two materials having different lattice constants; or (c) generating another tension in the solar cell by a shallow trench isolation filler, a high tensile/compressive stress silicon nitride layer and a combination thereof.

Structure and method of solar cell efficiency improvement by strain technology

The present disclosure passivates solar cell defects. Plasma immersion ion implantation (PIII) is used to repair the defects during or after making the solar cell. Hydrogen ion is implanted into absorption layer with different sums of energy to fill gaps of defects or surface recombination centers. Thus, solar cell defects are diminished and carriers are transferred with improved photovoltaic conversion efficiency.

Solar cell defect passivation method

A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read.

Memory formed by using defects

Growing community of inventors

Taipei, Taiwan

Chee Wee Liu