Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Industrial Technology Research Institute

Mediatek Corporation

National Yang Ming Chiao Tung University

National Applied Research Laboratories

Other

Macronix International Co., Ltd.

National Science Council

Powerchip Semiconductor Manufacturing Corporation

Chee-Wee Liu

Fang-Liang Lu

Ya-Jui Tsou

Pin-Shiang Chen

Chung-En Tsai

Chia-Che Chung

Samuel C Pan

Chih-Lin Wang

Zong-You Luo

Hung-Chih Chang

Shao-Yu Lin

Yu-Shiang Huang

Chien-Te Tu

Miin-Jang Chen

Min-Hung Lee

Liang-Chor Chung

Jhih-Yang Yan

I-Hsieh Wong

Kuen-Yu Tsai

Hung-Yu Yeh

Wen Hung Huang

Hsin-Cheng Lin

Yen-Ting Chen

Sheng-Ting Fan

Pang-Shiu Chen

Chih-Hsiung Huang

Hung-Yu Ye

Cheng-Yi Peng

Wei-Jen Chen

Yi-Chun Liu

Lih-Juann Chen

Sheng-Wei Lee

Kun-Wa Kuok

Jih-Chao Chiu

Der-Chuan Lai

Yi-Hsiu Hsiao

Shahaji B More

Cheng-Han Lee

Shih-Chieh Chang

Chih-Sheng Chang

Hsien-Hsin Lin

Chung-Yi Lin

Jin-Wei Shi

Wen-Kai Wan

Zing-Way Pei

Wen-Hsien Tu

Huang-Siang Lan

Shih-Ya Lin

Shu-Tong Chang

Yu-Jiun Peng

Yun-Ju Pan

Fon Yuan

Chia-Jung Tsen

Yen-Yu Chen

Teng-Hao Yeh

Ching-Fuh Lin

Wei-Chen Chen

Ming-Tzong Yang

Dai-Ying Lee

Cha-Hsin Lin

Yu-Min Hsu

Yu-Cheng Shen

Chin-Kun Wang

Kao-Feng Liao

Yuh-Ta Fan

Chun-Ti Lu

Wei-Fan Lee

Guang-Li Luo

Shing-Chii Lu

Yu-Chieh Lee

Meng-Chin Lee

Cheng-Yeh Yu

Shu-Han Hsu

Chun-Hung Lai

Meng-kun Chen

Wei-Shuo Ho

Cheng-Ya Yu

Sun-Rong Jan

Shu Tong Chang

Shing Chii Lu

Buo-Chin Hsu

Chung-Hsun Lin

Pang-Chun Liu

Zefu Zhao

Rachit Dobhal

Eknath Sarkar

Yichen Ma

Chun-Yi Cheng

Song-Ling Li

Tao Chou

Yu-Hung Liao

Tzu-Yao Lin

Hsuan-Yi Lin

Hui-Hsuan Wang

Chun-Lin Chu

A memory device includes a memory array, a first reference voltage circuit, a first read voltage control circuit and a first write voltage control circuit. The first reference voltage circuit is configured to provide a first reference voltage signal having a first voltage level to the memory array. The first read voltage control circuit is configured to adjust the first reference voltage signal to a second voltage level when the memory array is read. The first write voltage control circuit is configured to adjust the first reference voltage signal to a third voltage level when the memory array is written. The second voltage level is higher than the first voltage level, and the third voltage level is lower than the first voltage level.

Memory device adjusting reference voltage signal

A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

Memory device and formation method thereof

The present disclosure is directed to semiconductor structures with source/drain epitaxial stacks having a low-melting point top layer and a high-melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. Further, the semiconductor structure includes a source/drain epitaxial stack disposed in the recess, where the source/drain epitaxial stack has bottom layer and a top layer with a higher activated dopant concentration than the bottom layer.

Source and drain epitaxial layers

The method includes forming a sacrificial multi-layer stack including alternating first sacrificial layers and second sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layers to form first spaces each interposing two of the second sacrificial layers; depositing a first dielectric layer and a first electrode material in the first spaces; removing the second sacrificial layers to form second spaces each interposing two portions of the first electrode material; depositing a second dielectric layer and a second electrode material in the second spaces.

Capacitor and method for forming the same

A method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of sacrificial layers and a plurality of channel layers alternately arranged over the semiconductor substrate, and each of the sacrificial layers is a multi-layer film comprising a bottom epitaxial layer, a middle epitaxial layer over the bottom epitaxial layer, and a top epitaxial layer over the middle epitaxial layer, wherein the middle epitaxial layer has a lower germanium concentration than the bottom and top epitaxial layers; laterally recessing the sacrificial layers to form sidewall recesses alternating with the channel layers; forming inner spacers in the sidewall recesses; forming source/drain epitaxial structures on opposite sides of the channel layers.

Semiconductor device and manufacturing method thereof

A device includes a first channel structure, a second channel structure, and a gate structure. The first channel structure connects a first source region and a first drain region, and includes alternating stacking first semiconductor layers and second semiconductor layers. The second semiconductor layers have a width smaller than a width of the first semiconductor layers. The second channel structure connects a second source region and a second drain region. The second channel structure includes alternating stacking third semiconductor layers and fourth semiconductor layers. The fourth semiconductor layers have a width smaller than a width of the third semiconductor layers. The gate structure wraps around the first and second channel structures.

Fin field effect transistors (FINFET) device including a plurality of recessed regions alternating with unrecessed regions in channel stack

A method includes forming a fin over a substrate, the fin comprising alternately stacking first oxide-based semiconductor layers and second oxide-based semiconductor layers, removing the second oxide-based semiconductor layers to form a plurality of spaces each between corresponding ones of the first oxide-based semiconductor layers, and depositing in sequence a gate dielectric layer and a gate metal into the plurality of spaces each between corresponding ones of the second oxide-based semiconductor layers.

Semiconductor device with oxide-based semiconductor channel

An IC structure comprises an MTJ cell, a transistor, a first word line, and a second word line. The transistor is electrically coupled to the MTJ cell. The transistor comprises a first gate terminal and a second gate terminal independent of the first gate terminal. The first word line is electrically coupled to the first gate terminal of the transistor. The second word line is electrically coupled to the second gate terminal of the transistor. A resistance state of the MTJ cell is dependent on a first word line voltage applied to the first word line and a second word line voltage applied to the second word line, and the resistance state of the MTJ cell follows an AND gate logic or an OR gate logic.

Integrated circuit structure and fabrication thereof

A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Magnetoresistive memory device and manufacturing method thereof

A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Method for non-resist nanolithography

A photosensor provided herein includes a sensing structure and a microlens. The sensing structure includes an epitaxial layer, a deep trench and a scattering structure. The epitaxial layer has an illuminated surface and a non-illuminated surface. The deep trench isolation is located along an edge of the epitaxial layer. The scattering structure is embedded in the epitaxial layer and extends inwardly from the illuminated surface. The scattering structure includes a first circular ring pattern and a peripheral pattern. The deep trench isolation surrounds the scattering structure, the peripheral pattern is connected with the deep trench isolation and the first circular ring pattern is separated from the peripheral pattern and the deep trench isolation. The microlens is disposed on the epitaxial layer, wherein the illuminated surface of the epitaxial layer is relatively close to the microlens than the non-illuminated surface.

Photosensor having a scattering structure comprises circular ring and peripheral patterns

A semiconductor device includes a substrate, a semiconductor strip, an isolation dielectric, a plurality of channel layers, a gate structure, a plurality of source/drain structures, and an isolation layer. The semiconductor strip extends upwardly from the substrate and has a length extending along a first direction. The isolation dielectric laterally surrounds the semiconductor strip. The channel layers extend in the first direction above the semiconductor strip and arrange in a second direction substantially perpendicular to the substrate. The gate structure surrounds each of the channel layers. The source/drain structures are above the semiconductor strip and on either side of the channel layers. The isolation layer is interposed between the semiconductor strip and the gate structure and further interposed between the semiconductor strip and each of the plurality of source/drain structures.

Semiconductor device and method for forming the same

The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

Integrated circuit structure and method for forming and operating the same

A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Semiconductor device having doped work function metal layer

A device is provided. The device includes a memory cell and a first write assist circuit. The memory cell operates with a first supply voltage and a second supply voltage different from the first supply voltage. The first write assist circuit includes a first write assist switch and a second write assist switch that are coupled to the memory cell through a first data line. In a write operation of a data, having a first logic value, to the memory cell, the first write assist switch transmits the first supply voltage to the first data line in response to a first control signal, received at a control terminal of the first write assist switch and having a voltage level of the second supply voltage, when the second write assist switch is configured to be turned off.

Write assist circuit for memory device

Growing community of inventors

Taipei, Taiwan

Chee-Wee Liu