Altera Corporation

Chee Wai Yap

Boon Hong Oh

Muhamad Aidil Jazmi

Mark Webb

Joseph DeLaere

Circuitry and methods of operation thereof for video communication are described herein. The circuitry described herein may be programmable circuitry. The circuitry may include a receiver circuit and/or a transmitter circuit and one of the provided techniques includes receiving and/or transmitting video data. The receiver circuit may include a detector circuit that is used to determine the data rate of the received video data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. The data rate of the video data stream may be associated with a video standard. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit. The circuitry discussed herein can support multiple protocol data paths.

Multi-rate transceiver circuitry

Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.

A method and apparatuses for securing an integrated circuit (IC) with a self-destruction mechanism are provided. The IC has a tamper detect circuit that will detect unwanted or unauthorized access to the IC. The IC may store configuration and user data in a memory module. The memory module may be an internal or an external non-volatile or volatile memory source. Configuration and user data stored in the memory module is erased when a tamper condition is detected. The IC is powered down after the erase operation is completed. When the IC is powered down, data stored in a static random access memory (SRAM) module in the IC is erased. When the IC is powered up again, the IC will be in a non-operative state as the configuration data has been completely erased.

Integrated circuit with a self-destruction mechanism

Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.

Programmable logic device with a self-power down mechanism

An integrated circuit may include memory interface circuitry that interfaces with memory. The integrated circuit may include calibration circuitry and storage circuitry. The calibration circuitry may have a first configuration in which the calibration circuitry is formed from a first set of programmable logic regions that configure the calibration circuitry to generate and store calibration data at the storage circuitry. The calibration data may include strobe signal phase settings and read enable control signal timing settings. The calibration circuitry may have a second configuration in which the calibration circuitry is formed from a second set of programmable logic regions that configure the calibration circuitry to load the calibration data from the storage circuitry and to interface with the memory based on the calibration data. The calibration circuitry may occupy fewer programmable logic regions on the integrated circuit in the second configuration than in the first configuration.

Integrated circuits with improved memory interface calibration capabilities

A PLD having real-time in-system programmability (ISP) capability is provided. The PLD includes a configuration memory region into which the updated configuration is obtained. A user memory region stores the state for registers of the PLD. The configuration memory region communicates the updated configuration to a core logic region that includes a real-time ISP detection block that detects the initiation of a real-time ISP operation. A controller is in communication with the logic block. The PLD maintains register data by reading a state of the registers of the PLD/logic block and clamping the output pins before the core logic region is being updated. The state of the registers is saved in the memory region as directed by the controller. Upon completion of the update into the logic array, the registers of the PLD are cleared and a control signal from a memory interface triggers the controller to read stored the register data back from the memory and reload the registers. Upon the completion of reloading the registers, the output pins are released for normal device operation.

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Penang, Malaysia

Chee Wai Yap