Nxp Usa, Inc.

Chee Seng Foong

Trent Uehling

Tingdong Zhou

Nihaar N Mahatme

Nishant Lakhera

Akhilesh Kumar Singh

Andrew Jefferson Mawer

A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.

Device package substrate structure and method therefor

A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.

Packaged semiconductor device assembly

Growing community of inventors

Austin, TX, United States of America

Chee Seng Foong