Freescale Semiconductor,inc.

Nxp Usa, Inc.

University of Texas System

Nxp B.v.

Freescale Semiocnductor, Inc.

Chee Seng Foong

Lan Chu Tan

Navas Khan Oratti Kalandar

Wai Yew Lo

Kai Yun Yow

Trent Uehling

Aminuddin Ismail

Tingdong Zhou

Nishant Lakhera

Akhilesh Kumar Singh

Heng Keong Yip

Teck Beng Lau

Zi Song Poh

Leo M Higgins, Iii

Meng Kong Lye

Boon Yew Low

Nilabh Kumar Roy

Tim V Pham

James S Golab

Kesvakumar V C Muniandy

Kong Bee Tiu

Michael Cullinan

Chin Teck Siong

Ly Hoon Khoo

Anil Yuksel

Ruzaini B Ibrahim

Seng Kiong Teng

Wen Shi Koh

Yuan Zang

Lee Fee Ngion

Stanley Andrew Cejka

Norazham Mohd Sukemi

Tzu Ling Wong

Thoon Khin Chang

Kok Wai Mui

Lau Teck Beng

Low Boon Yew

Kim Chiew Ho

Bihua He

Bee Hoon Liau

Jin- Mei Liu

Jian- Hong Wang

Jin- Zhong Yao

Fu- Bin Song

Twila Jo Eichman

Kim Heng Tan

Sheng Ping Took

A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.

Device package substrate structure and method therefor

Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.

Package with conductive underfill ground plane

A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.

Hybrid package

Embodiments are provided herein for a substrate having one or more embedded traces and a method for fabricating one or more embedded traces. The method includes: forming a bump on a first major surface of a substrate, the bump having a height measured from the first major surface to a top surface of the bump; forming a trace comprising: a lower trace portion that directly contacts the first major surface, a sidewall trace portion that directly contacts at least one sidewall of the bump, and an upper trace portion that directly contacts the top surface of the bump; depositing a blanket dielectric layer over the trace; and etching away a top portion of the blanket dielectric layer to expose a top surface of the upper trace portion.

Method of fabricating embedded traces

A microscale selective laser sintering (&#x3bc;-SLS) that improves the minimum feature-size resolution of metal additively manufactured parts by up to two orders of magnitude, while still maintaining the throughput of traditional additive manufacturing processes. The microscale selective laser sintering includes, in some embodiments, ultra-fast lasers, a micro-mirror based optical system, nanoscale powders, and a precision spreader mechanism. The micro-SLS system is capable of achieving build rates of at least 1 cm/hr while achieving a feature-size resolution of approximately 1 &#x3bc;m. In some embodiments, the exemplified systems and methods facilitate a direct write, microscale selective laser sintering &#x3bc;-SLS system that is configured to write 3D metal structures having features sizes down to approximately 1 &#x3bc;m scale on rigid or flexible substrates. The exemplified systems and methods may operate on a variety of material including, for example, polymers, dielectrics, semiconductors, and metals.

Micro-selective sintering laser systems and methods thereof

Embodiments of a substrate are provided herein, which include: a first metal plane and a second metal plane in a first metal layer, the first and second metal planes laterally separated by a first gap of dielectric material; and a third metal plane and a fourth metal plane in a second metal layer vertically adjacent to the first metal layer, the third and fourth metal planes laterally separated by a second gap of dielectric material, wherein the second gap comprises a first laterally-shifted gap portion and a second laterally-shifted gap portion, the first laterally-shifted gap portion is laterally offset from a vertical footprint of the first gap in a first lateral direction, and the second laterally-shifted gap portion is laterally offset from the vertical footprint of the first gap in a second lateral direction opposite the first lateral direction.

Substrate dielectric crack prevention using interleaved metal plane

A 'universal' substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.

Substrate interconnections for packaged semiconductor device

A method of making a packaged integrated circuit device includes forming a lead frame with leads that have an inner portion and an outer portion, the inner portion of the lead is between a periphery of a die pad and extends to one end of openings around the die pad. The outer portion of the leads are separated along their length almost up to an opposite end of the openings. Leads in a first subset of the leads alternate with leads in a second subset of the leads. The inner portion of the first subset of the leads is bent. The die pad, the inner portion of the leads, and only a first portion of the openings adjacent the inner portion of the leads are encapsulated. A second portion of the openings and the output portions of the leads form a dam bar for the encapsulating material.

Packaged semiconductor device having a lead frame and inner and outer leads and method for forming

Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package comprising a first die and a second die, wherein the first die and the second die are laterally positioned to one another, and the first die and the second die are laterally separated from one another by mold compound; and a conductive trace formed between a first conductive surface on an exposed surface of the first die and a second conductive surface on an exposed surface of the second die, wherein the conductive trace is laser sintered directly on the first conductive surface, on a portion of the exposed surface of the first die, on a portion of a top surface of the mold compound, on a portion of the exposed surface of the second die, and on the second conductive surface.

Laser sintered interconnections between die

A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.

Universal BGA substrate

A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.

Circuit substrate and method of manufacturing same

A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.

Substrate for alternative semiconductor die configurations

A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.

Semiconductor device package with organic interposer

A method for assembling a thin, flexible integrated circuit (IC) device includes using an etched contoured lead frame having raised features. A die is attached to the lead frame to form a sub-assembly that is then selectively coated with a low-modulus gel. The sub-assembly is covered with a temporary mask for sputter deposition of a metallic seed layer for interconnects between the die and the raised features. The mask is removed and more robust metal interconnects are grown over the seed paths using electroplating. The sub-assembly top is then coated with another gel layer. The bottom of the sub-assembly and of the contoured lead frame is removed, which transforms the raised features into leads. The newly exposed bottom of the sub-assembly is covered with a third layer of gel to complete assembly of the packaged device.

Flexible packaged integrated circuit

An interposer for a packaged semiconductor device is formed by applying an encapsulant to (e.g., by overmolding or applying lamination of tapes to) a perforated metal foil having vertical metal tabs that form the vertical metal vias in the interposer. A solid metal foil can be stamped using a micro-stamping tool to form the perforated foil and vertical tabs. Bump pads and/or re-distribution layer (RDL) traces are formed (e.g., using wafer fabrication processes or by applying flexible tape RDL layers) on the top and back sides of the foil to complete the manufacturing process. Such interposers can be cheaper to manufacture than conventional interposers having silicon or glass substrates with through-silicon vias (TSVs) formed using wafer fabrication processes.

Interposer with overmolded vias

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Chee Seng Foong