Utac Headquarters Pte. Ltd.

Chee Kay Chow

Teddy Joaquin Carreon

Hua Hong Tan

Kriangsak Sae Le

Wedanni Linsangan Micla

Dzafir Bin Mohd Shariff

Enrique Jr Sarile

Dennis Fernandez Tresnado

Mauro Jr Dionisio

Thian Hwee Tan

Mario Arwin Fabian

Tim Thian Hwee Tan

Antonino Ii Milanes

Boon Pek Liew

Kian Soo Lim

Ming Koon Ang

Enrique Sarile, Jr

A wafer adaptor ring assembly for adapting an adapted sized wafer for plasma dicing by a plasma etch chamber designed for dicing a designed sized wafer, which is larger than the adapted sized wafer is disclosed. The wafer adaptor ring assembly includes a primary wafer ring designed for plasma dicing the designed sized wafer by the plasma, an adhesive sheet attached to a bottom surface of the primary wafer ring, and an adapted sized wafer disposed on the adhesive sheet between the primary wafer ring and the adapted sized wafer. A method for forming the wafer adaptor ring assembly is also disclosed.

Wafer adaptor for adapting different sized wafers

A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed. The discontinuity enhances adhesion of the encapsulant to the protective cover.

Reliable semiconductor packages

A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein. A sensor chip having an image sensing element is disposed on a top surface of the package substrate, and an integrated circuit is mounted to a bottom surface of the package substrate. The integrated circuit is a flip-chip assembly. The sensor chip is electrically connected to the integrated circuit. An adhesive material bonds a transparent covering member to the sensor chip to enclose the image sensing element.

Image sensor with processor package

A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes first and second surfaces. The through interposer vias extend from the first surface to the second surface of the interposer. The interposer with the through interposer vias enable attachment and electrical coupling of a die having very fine contact pitch to an external device having relatively larger contact pitch. At least a first die is mounted on at least one die attach region on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with CTE similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. A bonding process which does not require a reflow process is performed to form connections between the first die and interposer.

Semiconductor packages and methods of packaging semiconductor devices

Growing community of inventors

Singapore, Singapore

Chee Kay Chow