Marvell International Limited

Marvellworld Trade Ltd.

Skhynix Inc.

Chee Hoe Chu

Wei Zhou

Po-Chien Chang

Ping Zheng

William Lo

Runsheng He

Gang Wang

Haoli Qian

Hui Wang

Yi-Chun Chen

Jeffrey Choun

Lihan Chang

Xinhai Kang

Qun Zhao

Jinliang Mao

Hsing-Yi Chiang

Jin-Nan Liaw

Alexander Geoffrey Jensen

Robyn Jie Li

Joseph R Goodearly

Chi-Chih Lin

A drive loading jig, drive carrier assembly and method of using the same to insert and remove a drive from a host reduce the likelihood of a drive being damaged during insertion or removal. Such a drive loading jig has side walls with respective slots and a rear wall joining the side walls. Each of the slots includes multiple restraining walls to restrain a drive, when positioned in the jig, from bending with respect to a plane parallel to a major surface of the drive and from moving in a direction substantially perpendicular to the major surface. Stoppers formed in the side walls or rear wall define a maximum insertion depth of the drive. An alignment key-way on the loading jig is used to align the drive in the proper orientation prior to inserting the drive into the loading jig.

Drive loading jig for memory drives

An apparatus for determining an eye mask of a device under test (DUT) which is configured to receive a data bit stream signal including a threshold level value and output a data bit stream output signal. The apparatus includes an input unit configured to receive the data bit stream output signal provided by the DUT, an evaluation unit configured to evaluate the received data bit output signal and provide an evaluation result, and a controller configured to change the threshold level value in response to the evaluation result. The apparatus is integrated into the DUT and can operates autonomously without multiple interactions with a tester.

Eye opening hardware offloading

Embodiments of the present invention provide a method comprising performing an operation on a first flash drive of a plurality of flash drives configured in a parallel flash drive architecture, wherein the operation occupies a flash controller corresponding to the first flash drive, sending a signal to a processor coupled with the parallel flash drive architecture to indicate that the flash controller is occupied, and writing data to two or more of the plurality of flash drives, other than the first flash drive, by striping the data amongst the two or more of the plurality of flash drives in response to the signal to the processor. Other embodiments may be described and/or claimed.

Operation aware striping in parallel drives

This disclosure describes techniques and/or apparatuses for reducing the total time used to boot up a computer and load applications onto the computer.

Preloading an application while an operating system loads

A single integrated circuit comprises one or more functional modules; a bus port; a bus in communication with the one or more functional modules and the bus port; and a bus tracer disposed within the integrated circuit and configured to capture activity on the bus. A method for a single integrated circuit comprising a bus comprises capturing, in a bus tracer disposed within the single integrated circuit, activity on the bus; and providing, through a bus port of the single integrated circuit, the activity captured by the bus tracer.

In-chip bus tracer

In aspects of serial interface for FPGA prototyping, an advanced crossbar interconnect (AXI) bridge structure enables serial data communication between field programmable gate arrays (FPGA) in a system-on-chip (SoC). The AXI bridge structure includes a parallel interface configured to receive AXI data signals from an AXI component implemented at a first FPGA. A transmit (TX) engine is configured to packetize the AXI data signals into an AXI data packet, and transmit the AXI data packet to a second FPGA via a serial link. The AXI bridge structure also includes a receive (RX) engine configured to receive an additional AXI data packet from the second FPGA via the serial link, and extract AXI data signals from the additional AXI data packet. The parallel interface is further configured to provide the additional AXI data signals to the AXI component.

Serial interface for FPGA prototyping

A flash controller includes a PCIe interface, a DMA engine module, a memory control module, and a flash control module. The PCIe interface communicates with a host device and receives first data from the host device. The first data is formatted using a native PCIe protocol and includes a first key-value pair that is to be stored in first memory. The first memory includes flash memory. The first key-value pair includes a first unique number and the first data. The PCIe interface receives second data from the first memory and transmits the second data from the host device. The second data is formatted using the native PCIe protocol and includes a second key-value pair. The second key-value pair includes a second unique number and the second data. The DMA engine module transfers the first and second data between the PCIe interface, the first memory and second memory.

Data storage methods and apparatus

An integrated circuit ('IC') may have flash memory circuitry associated with it. The IC may also have controllable routing circuitry for routing signal information (1) between the flash memory circuitry and any one of a plurality of signal ports of the IC, or (2) between various ones of those signal ports. Multiple instance of such ICs and their associated flash memory circuitries may be connected to one another via the above-mentioned signal ports to provide flash memory storage systems of any size in which data can be routed in and out at least partly via the controllable routing circuitries of the various ICs.

Multiple port routing circuitry for flash memory storage systems

A receiver including recovery, error, and control modules. The recovery module: receives a data signal and an offset value; based on a coefficient, equalizes the data signal to generate an equalized signal; and generates a recovered signal based on the equalized signal. The recovered signal includes data recovered by the recovery module. The error module generates an error value based on a difference between the equalized signal and a threshold. The control module, based on the offset value, the recovered signal, and the error value: generates the coefficient; determines the threshold; and determines a characteristic of an eye diagram of the recovered signal. The recovered signal has a non-repeating pattern such that overlaid traces of the recovered signal are in a shape of an eye and provide the eye diagram. The overlaid traces include jitter. The control module generates the coefficient to reduce an amount of the jitter.

Method and apparatus for reducing jitter in overlaid traces of an eye diagram of a recovered signal generated based on a received data signal

A flash memory file system including a plurality of flash modules. Each of the plurality of flash modules includes a respective cache memory, a respective flash memory, and a respective flash controller in communication with the respective cache memory and the respective flash memory. A first flash module of the plurality of flash modules is configured to receive a file lookup message including a path name for file data stored on a second flash module of the plurality of flash modules. A third flash module of the plurality of flash modules is configured to select the second flash module based on the path name and a directory table, and generate a file metadata message responsive to the file lookup message. The file metadata message identifies the second flash module as containing the file data.

Systems and methods for operating a flash memory file system

A peripheral device includes a host interface, a power interface, a switch, a control module, and a regulator. The host interface transfers data between the peripheral device and a host. The power interface receives power from a power source. The power source is separate from the peripheral device and the host. The control module monitors the host interface and generates a control signal to transition the switch from a first state to a second state when the host interface does not receive an expected signal from the host. The regulator powers the control module and a circuit of the peripheral device based on the power received from the power source. The control module is separate from the circuit. The switch activates the control module, the regulator and the circuit when in the first state and deactivates the control module, the regulator and the circuit when in the second state.

Power smart peripheral devices with external power supplies

A serializer/deserializer for a network device includes a data module configured to generate parallel data and side band data. A serializer is configured to convert the parallel data to serialized data for transmission over a communication channel, wherein the serialized data includes a serial data waveform. A side band transmission module is configured to generate a clock signal, inject the clock signal with side band data to generate a modulated clock signal, and apply the modulated clock signal to the serialized data to generate a modified serial data waveform. The modified serial data waveform includes the serialized data and the side band data and includes pulses with an increased pulse width and/or a decreased pulse width with respect to the serial data waveform. The serializer is configured to transmit, over the communication channel, the modified serial data waveform including the serialized data and the side band data.

System and method for side band communication in SERDES transmission/receive channels

Apparatus having corresponding methods and computer-readable media comprise: a plurality of flash modules, wherein each of the flash modules comprises a cache memory; a flash memory; and a flash controller in communication with the cache memory and the flash memory; wherein the flash controller of a first one of the flash modules is configured to operate the cache memories together as a global cache; wherein the flash controller of a second one of the flash modules is configured to operate a second one of the flash modules as a directory controller for the flash memories.

Systems and methods for operating a plurality of flash modules in a flash memory file system

Apparatus having corresponding methods and computer-readable media comprise: a phase detector configured to generate an error signal representing a phase difference between a recovered spread-spectrum clock signal and a serial data stream that includes a spread-spectrum clock signal; and a phase selector configured to provide the recovered spread-spectrum clock signal based on an error signal from a current spread-spectrum cycle of the spread-spectrum clock signal and an error signal from a previous spread-spectrum cycle of the spread-spectrum clock signal.

Growing community of inventors

San Jose, CA, United States of America

Chee Hoe Chu