Semiconductor Components Industries, LLC

Chee Hiong Chew

Atapol Prajuckamol

Yusheng Lin

Francis J Carney

Yushuang Yao

Soon Wei Wang

Eiji Kurose

Michael John Seddon

Stephen St Germain

Vemmond Jeng Hung Ng

Erik Nino Tolentino

Swee Har Khor

Hui Min Ler

Shutesh Krishnan

Darrell D Truhitte

Phillip Celaya

Yenting Wen

Saat Shukri Embong

Azhar Aripin

Jatinder Kumar

Aik Chong Tan

Jin Yoong Liong

Tian Hing Lim

James Price Letterman, Jr

Qing Yang

Sadamichi Takakusaki

Yong Liu

Brian A Webb

Albert J Laninga

Liangbiao Chen

How Kiat Liew

Olaf Zschieschang

Roger Paul Stout

Boon Huat Lim

Jinchang Zhou

Kenneth Teik Kheong Low

Asif Jakwani

Dave Culbertson

Sravan Vanaparthy

Shan Chong Tan

Santhiragasen Al Sengram Pillay

Silnore Tejero Sabando

Chuncao Niu

Khiengkrai Khusuwan

Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.

Silicon-on-insulator die support structures and related methods

A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

Leadless semiconductor packages, leadframes therefor, and methods of making

A module includes a power circuit enclosed in a casing. A first power terminal and a second power terminal of the power circuit each extend to an exterior of the casing. The first power terminal and the second power terminal separated by a gap are disposed in a stack on the exterior of the casing.

Stacked power terminals in a power electronics module

A circuit module includes a substrate with a patterned metal surface. The patterned metal surface includes a conductive terminal pad, a first conductive pad, and a second conductive pad that is non-adjacent to the conductive terminal pad. A first circuit portion is assembled on the first conductive pad and a second circuit portion is assembled on the second conductive pad. A conductive bridge electrically couples the conductive terminal pad and the second conductive pad. The conductive bridge includes an elevated span extending above and across the first conductive pad.

Power circuit module

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Die sidewall coatings and related methods

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

Semiconductor packages with die including cavities and related methods

Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Low stress asymmetric dual side module

Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.

Semiconductor package and related methods

Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate and a plurality of press-fit pins. The press-fit pins are molded into and fixedly coupled with the case. The pins are also electrically and mechanically coupled to the substrate.

Semiconductor package system and related methods

Implementations of a substrate may include an electrically insulative layer having a first largest planar side and a second largest planar side opposing the first largest planar side; a first electrically conductive layer coupled to the first largest planar side and including a first scalloped edge having a first pattern; and a second electrically conductive layer coupled to the second largest planar side and including a second scalloped edge having a second pattern. The first pattern and the second pattern may alternate along at least one edge of the first largest planar side and at least one edge of the second largest planar side, respectively.

Substrates and related methods

According to an aspect, a power electronic module includes a substrate, a semiconductor die coupled to the substrate, and a clip member configured to secure the semiconductor die to the substrate, where the clip member includes a base portion having a surface coupled to the semiconductor die, an extender portion that extends from the base portion, where the extender portion includes a contact portion coupled to the substrate, and at least one protrusion that extends from the base portion or the extender portion.

Clip design and method of controlling clip position

Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

Semiconductor package with wettable flank and related methods

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Seremban, Malaysia

Chee Hiong Chew