Samsung Electronics Co., Ltd.

Chea-Ouk Lim

Yong-jun Lee

Tae-Hui Na

Makoto Hirano

Bilal Ahmad Janjua

Jun-Gyu Lee

A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

Memory devices, memory systems and methods of operating memory devices

An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.

Growing community of inventors

Hwaseong-si, South Korea

Chea-Ouk Lim