Mediatek Corporation

Che-Yuan Jao

Sheng-Ming Chang

Ching-Chih Li

Chen-Feng Chiang

Chun-Wei Chang

Nan-Jang Chen

Nan-Cheng Chen

Chien-Chung Chen

Rei-Fu Huang

Hung-Sung Li

Chuan-Cheng Hsiao

I-Cheng Lin

Chia-Hsien Liu

A control circuit comprising a driving circuit, which comprises a voltage adjusting circuit for generating a control voltage, and comprises a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. The control circuit further comprises: a candidate voltage selecting circuit, for outputting one of a plurality of candidate voltages; and a voltage selecting circuit, for outputting one of the candidate voltage output from the candidate voltage selecting circuit and a ground voltage as the bias voltage.

Control circuit and control system

One embodiment of the present application discloses a control circuit comprising a driving circuit which comprises a voltage adjusting circuit, a first transistor and a second transistor. The first transistor comprises: a first terminal; a second terminal; and a control terminal, for receiving a bias voltage generated from at least operating voltage of the control circuit. The second transistor comprises: a first terminal, coupled to a second terminal of the first transistor; a second terminal, for receiving a first predetermined voltage; and a control terminal, for receiving the control voltage. A control system comprising the control circuit is also disclosed.

A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer.

Receiving circuits for core circuits

A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

Leadframe package for high-speed data rate applications

The present invention provides a semiconductor device capable of eliminating voltage (IR) drop of a semiconductor die inside the semiconductor device and a fabricating method of the semiconductor device. The semiconductor device comprises the semiconductor die, and the semiconductor die comprises a first surface area, a plurality of first pads potentially equivalent to each other, a passivation layer, a plurality of first openings, and a first conducting medium layer. The passivation layer is disposed on the plurality of first pads. The plurality of first openings is formed on the passivation layer, and utilized for exposing the plurality of first pads. The first conducting medium layer is formed on the first surface area, and utilized for fulfilling the plurality of first openings to connect the plurality of first pads.

Semiconductor device and fabricating method thereof

An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and a first input node coupled to a first power source which supplies a first reference voltage acting as a programming voltage of the e-fuse macro. The switch device connects the first power source to the e-fuse units when the e-fuse macro is operated under a programming mode.

E-fuse apparatus for controlling reference voltage required for programming/reading e-fuse macro in an integrated circuit via switch device in the same integrated circuit

A semiconductor chip includes a die mounted on a packaging substrate. The die includes a semiconductor substrate; inter-metal dielectric layers on the semiconductor substrate; levels of metal interconnection, wherein at least two potential equivalent metal traces are formed in a level of the metal interconnection; a passivation layer disposed over the two metal traces, wherein two openings are formed in the passivation layer to expose portions of the two metal traces; a conductive member externally mounted on the passivation layer between the two openings; and a redistribution layer formed over the conductive member.

Semiconductor chip having conductive member for reducing localized voltage drop

An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.

Growing community of inventors

Hsinchu, Taiwan

Che-Yuan Jao