Au Optronics Corporation

Auo Corporation

Au Potronics Corp.

Che-Wei Tung

Wei-Li Lin

Chia-Heng Chen

Che-Chia Chang

Yu-Chieh Kuo

Shu-Fang Hou

Mei-Yi Li

Yu-Hsun Chiu

Ming-Hung Chuang

Cheng-Hsing Lin

Yu-Zuo Lin

Chia-Ming Chang

Yi-Fan Chen

Chen-Chi Lin

Shang-Jie Wu

Jui-Chi Lo

Chia-En Wu

Chun-Huan Chang

Ming-Yang Deng

Chen-Ying Chou

Keng-Chuan Cheng

Yen-Wei Yeh

Chin-Hsien Chou

Yan-Ting Chen

Shu-Han Chang

Chun-Shiang Dai

Ming-Hsien Lee

En-Chih Liu

Shu-Wen Tzeng

Chin-Hao Chang

Wei-Kai Huang

A display apparatus is provided. The display apparatus includes a display module and multiple light-emitting driving circuits. Each of the light-emitting driving circuits includes a timing control circuit and a driving circuit. The timing control circuit receives multiple clock signals and a previous light-emitting timing signal to provide a light-emitting timing signal and an internal voltage. The driving circuit receives a first phase signal among multiple phase signals and the internal voltage to provide a light-emitting driving signal to the display module based on the first phase signal and the internal voltage. The phase signals all present disabled levels during a vertical blank period.

Display apparatus

A display includes a first light emitting device. The first light emitting device includes a first switch and a second switch. The first switch is configured to adjust a first node according to a first clock signal. The second switch is configured to generate a first light emitting signal according to a first voltage signal. A control end of the second switch is coupled to the first node. The first clock signal switches between a first voltage level and a second voltage level. The first voltage signal has a third voltage level. The third voltage level is more than one of the first voltage level and the second voltage level and is less than the other one of the first voltage level and the second voltage level.

Display

A display device and a driving method thereof are provided. In the display device, a display panel has multiple first pixel rows and multiple second pixel rows arranged alternately. In a first time interval, a first gate driver sequentially drives the first pixel rows using a first driving method. In a second time interval, a second gate driver sequentially drives the second pixel rows using the first driving method. In a third time interval, a third gate driver sequentially drives the first pixel rows using a second driving method. In a fourth time interval, a fourth gate driver sequentially drives the second pixel rows using the second driving method. One of the first driving method and the second driving method is a pulse amplitude modulation driving method, and the other of the first driving method and the second driving method is a pulse width modulation driving method.

Display device and driving method thereof

A display panel and a pixel circuit thereof are provided. The pixel circuit includes a driving current generator, a pulse width signal generator, a voltage provider, and a current enabler. The driving current generator provides a driving current. The pulse width signal generator includes an output switch. The output switch is controlled by a control signal, and provides a pulse width signal according to the control signal. The voltage provider adjusts the control signal according to a data write-in signal and a pulse width modulation enable signal. The current enabler provides the driving current to a lighting component according to the pulse width signal and an amplitude modulation enable signal.

Display panel and pixel circuit thereof

A driving circuit includes an S stage register, a first connect line, an (S+A) stage register and a second connect line. The S stage register receives an S stage control signal through a first switch unit and a second switch unit, so that the S stage register performs voltage regulation and outputs an S stage scan signal. The first connect line is electrically connected to the first switch unit of the S stage register. A third switch unit of the (S+A) stage register is electrically connected to the first connect line and a fourth switch unit of the (S+A) stage register for receiving the S stage scan signal, so that The (S+A) stage register performs voltage regulation. The second connect line is electrically connected to the second switch unit of the S stage register and the fourth switch unit of the (S+A) stage register.

Driving circuit with multiple stage registers performing voltage regulation

A scan driver circuit including shift register units and gate control circuits is provided. The shift register units are in a peripheral area of a display panel, and for receiving first clock signals. The gate control circuits are in an active area of the display panel, and for receiving second clock signals. Each shift register unit is coupled with corresponding N of the gate control circuits, and for providing a corresponding one of the first clock signals as a control signal to the corresponding N of the gate control circuits. The corresponding N of the gate control circuits are coupled with corresponding M of gate lines. The corresponding N of the gate control circuits are for providing, according to the control signal, corresponding M of the second clock signals as M gate signals to the corresponding M of gate lines, in which M and N are positive integers.

Display panel and scan driver circuit thereof suitable for narrow border application

A display panel is provided. The display panel includes a plurality of scan lines and a gate driving circuit. The scan lines are disposed on the display panel along a first direction, and respectively provide a plurality of gate driving signals. The gate driving circuit is disposed on a first side of the display panel along a second direction. The second direction intersects the first direction. The gate driving circuit includes a plurality of bias generators and a plurality of signal output circuits. The signal output circuits are divided into a plurality of groups. The bias generators respectively correspond to the groups. The bias generators generate a plurality of first bias voltages. The groups generate the gate driving signals respectively according to the first bias voltages.

Display panel with reduced border area improving charging and discharging capacities of gate driving circuit

The present disclosure relates to a driving circuit including a pulse amplitude modulation (PAM) circuit and a pulse width modulation (PWM) circuit. The PAM circuit includes a first transistor, a first capacitor, and a second transistor. The PWM circuit includes a second capacitor, a third transistor, and a fourth transistor. The first capacitor's first terminal is connected to the first transistor's gate. The second transistor's first terminal is connected to the first capacitor's first terminal, and the second transistor's second terminal is connected to the first transistor's second terminal. The third transistor's gate is connected to the second capacitor's second terminal. The fourth transistor's first terminal is connected to the third transistor's gate, the fourth transistor's second terminal is connected to the third transistor's second terminal, and the fourth transistor's gate is connected to the second transistor's gate and configured to receive a first control signal.

Driving circuit and driving method

A driving circuit includes a S stage register, a first connect line, a (S+A) stage register and a second connect line. The S stage register receives a S stage control signal through a first switch unit and a second switch unit, so that the S stage register performs voltage regulation and outputs a S stage scan signal. The first connect line is electrically connected to the first switch unit of the S stage register. A third switch unit of the (S+A) stage register is electrically connected to the first connect line and a fourth switch unit of the (S+A) stage register for receiving the S stage scan signal, so that The (S+A) stage register performs voltage regulation. The second connect line is electrically connected to the second switch unit of the S stage register and the fourth switch unit of the (S+A) stage register.

A display panel has a display region, an external circuit region located at an edge of the display panel, and a first and second wiring regions. The first wiring region is located between the second wiring region and the external circuit region. The display panel includes a pixel array, gate driving circuit groups disposed between the second wiring region and the display region, first signal line groups extended from the external circuit region to the first and second wiring region, and second signal line groups extended from the second wiring region and connected to the corresponding gate driving circuit groups. In the second wiring region, a first portion of the first signal line groups overlapped with the second signal line groups has a first width, and a second portion thereof not overlapped with the second signal line groups has a third width which is larger than the first width.

Display panel having a grading wiring design

A shift register includes a control circuit, a switching circuit, a driving circuit, and a pull-down circuit. The control circuit is configured to output a control signal having a high level during a pull-up period and a voltage-regulating period respectively. The switching circuit is configured to provide a control voltage according to the control signal and a front stage signal outputted by a front x-stage shift register during the pull-up period. The driving circuit is configured to generate a driving signal according to the control voltage provided by the switching circuit, and output a home stage scan signal based on the driving signal. The pull-down circuit is configured to pull down a voltage level of the driving signal according to a scan signal outputted by a rear y-stage shift register during a pull-down period. The switching circuit is configured to regulate the driving signal and the home stage scan signal.

Shift register and control method thereof

A shift register includes a first voltage stabilizing unit, a second voltage stabilizing unit, a main pull-down unit and a main pull-up unit. The first voltage stabilizing unit is used to pull a first driving control signal to a low voltage terminal when a first stabilizing control signal is high. The second voltage stabilizing unit is used to pull the first driving control signal to the low voltage terminal when a second stabilizing control signal is high. The main pull-down unit includes a first sub-pull-down unit controlled by a second gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a first display mode, and a second sub-pull-down unit controlled by a third gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a second display mode. The main pull-up unit is used for pulling up a first gate-terminal signal.

Shift register pulling control signals according to display mode

A shift register includes a plurality of stages of shift register circuit. Each stage of shift register circuit includes a first switch, an input circuit, a pull-down circuit, and a pull-down voltage regulator circuit. The first switch is used to output a scan signal according to a voltage level of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a signal from a previous M-th stage of shift register circuit. The pull-down circuit is used to pull down the voltage level of the node according to the clock signal and a signal from a following L-th shift register circuit and reduce current leakage at the node. The pull-down voltage regulator circuit is used to pull down the voltage levels of the node and the scan signal according to the voltage level of the node.

Shift register and method of driving shift register

A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.

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Hsin-Chu, Taiwan

Che-Wei Tung