Macroblock, Inc.

Realtek Semiconductor Inc.

National Taiwan University

National Yang Ming Chiao Tung University

Altek Corporation

Mitac Computing Technology Corporation

Moai Electronics Corporation

Che-Wei Chang

Chi-Min Hsieh

Chen-Yuan Kuo

Wei-Hsiang Cheng

Si-Chen Lee

Chung-Ming Chen

Wan-Jou Lee

Yu-Chun Chien

Chia-Yen Lee

Jian-Ru Lin

Kai-Yin Liu

Shih-Hsiung Huang

Chih-Cheng Lin

Edward Yi Chang

Liang-Huan Lei

Wei-Hua Chieng

Shuei-Lin Chen

Tsung-Lin Chen

Lon-Kou Chang

Shyr-Long Jeng

Cheng-Pang Chan

Stone Cheng

Chia-Ho Pan

Sheng-Hsiung Lin

Shih-Hsiun Huang

Ting-Ta Chiang

Li-Hsiang Chan

Chin-Hao Tu

Ming-Jia Wu

Shi-Jie Liao

Yi-Hao Hong

Chi-Hsing Wang

Hsin-Ta Huang

Bei-Chuan Chen

A scan-type display apparatus includes an LED array and a scan driver. The LED array has a common cathode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The scan driver includes multiple scan driving circuits. Each scan driving circuit includes a voltage generator and a detector. The voltage generator has an output terminal that is connected to the scan line corresponding to the scan driving circuit, and is configured to output one of a common voltage and a clamp voltage at the output terminal of the voltage generator. The detector is connected to the output terminal of the voltage generator, and generates a detection signal that indicates whether any one of the LEDs connected to the scan line corresponding to the scan driving circuit is short circuited based on a voltage at the output terminal of the voltage generator and a detection timing signal.

Scan-type display apparatus capable of short circuit detection, and scan driver thereof

A scan-type display apparatus includes an LED array and a data driver. The LED array has a common anode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The data driver includes multiple data driving circuits, each of which includes a current driver and a detector. The current driver has an output terminal connected to the data line corresponding to the data driving circuit, and outputs one of a drive current and a clamp voltage at the output terminal of the current driver based on a pulse width control signal. The detector is connected to the current driver, and generates a detection signal that indicates whether any one of the LEDs connected to the data line corresponding to the data driving circuit is short circuited based on a detection timing signal and a feed-in voltage related to a voltage at the output terminal of the current driver.

Scan-type display apparatus capable of short circuit detection, and data driver thereof

A scan-type display apparatus includes an LED array and a scan driver. The LED array has a common anode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The scan driver includes multiple scan driving circuits. Each scan driving circuit includes a voltage generator and a detector. The voltage generator has an output terminal that is connected to the scan line corresponding to the scan driving circuit, and is configured to output one of an input voltage and a clamp voltage at the output terminal of the voltage generator. The detector is connected to the output terminal of the voltage generator, and generates a detection signal that indicates whether any one of the LEDs connected to the scan line corresponding to the scan driving circuit is short circuited based on a voltage at the output terminal of the voltage generator and a detection timing signal.

A scan-type display apparatus includes an LED array and a data driver. The LED array has a common cathode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The data driver includes multiple data driving circuits, each of which includes a current driver and a detector. The current driver has an output terminal connected to the data line corresponding to the data driving circuit, and outputs one of a drive current and a clamp voltage at the output terminal of the current driver based on a pulse width control signal. The detector is connected to the current driver, and generates a detection signal that indicates whether any one of the LEDs connected to the data line corresponding to the data driving circuit is short circuited based on a detection timing signal and a feed-in voltage related to a voltage at the output terminal of the current driver.

A display system includes a light emitting array and a driving device. The light emitting array includes multiple scan lines, multiple drive lines and multiple light emitting elements. The driving device includes a controller, a charge balance line and a charge sharing circuit. The controller generates a control output. The charge sharing circuit is coupled to the drive lines, the charge balance line and the controller, and receives the control output from the controller. With respect to each of the drive lines, the charge sharing circuit is operable, based on the control output, to establish or not establish an electrical connection between the drive line and the charge balance line.

Display system and driving device thereof

Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.

Voltage reference buffer circuit

A display system includes an LED array and a driving device. The driving device includes a current driver, a scan selector and a capacitor. The current driver is connected to drive lines of the LED array, and provides a plurality of driving current signals respectively to the drive lines. The scan selector is connected to scan lines of the LED array, and has a first terminal that is configured to receive an input voltage, and a second terminal. The scan selector outputs the input voltage to a selected one of the scan lines, and outputs a clamp voltage provided at the second terminal thereof to the other ones of the scan lines. The capacitor has a first terminal, and a second terminal that is connected to the second terminal of the scan selector.

Display system capable of eliminating cross-channel coupling problem, and driving device thereof

A voltage control device includes an output module and a control module. The output module provides an output current at an output terminal thereof based on a control voltage. The control module includes a comparing circuit, a capacitor, a charging circuit and a discharging circuit. The comparing circuit compares a to-be-compared voltage, which is associated at least with a to-be-controlled voltage at the output terminal of the output module, with a predetermined reference voltage to generate a comparison signal. The capacitor provides the control voltage. The charging circuit is operable to charge the capacitor based on the comparison signal. The discharging circuit is operable to discharge the capacitor based on the comparison signal.

Voltage control device with gate capacitor charging and discharging

A successive approximation register (SAR) analog-to-digital converting method includes executing a sampling operation and a comparing operation according to a conversion clock by using an SAR analog-to-digital converter (ADC) to convert an analog input signal into a digital output signal, and resetting a sampling and digital-to-analog converting circuit of the SAR ADC when a SAR procedure of the comparing operation is completed.

Successive approximation register (SAR) analog-to-digital converting circuit and method thereof

An electronic apparatus includes a voltage-controlled oscillator and a biasing circuit. The voltage-controlled oscillator includes varactors. The voltage-controlled oscillator is configured to output an oscillating frequency at a first temperature. The biasing circuit electrically coupled with the varactors is configured to provide a first biasing voltage to the varactors at the first temperature, and provide a second biasing voltage to the varactors at a second temperature, in which the varactors have a first temperature coefficient, and the biasing circuit generates the first biasing voltage and the second biasing voltage according to values of the first temperature coefficient and a second temperature coefficient.

Electronic apparatus and controlling method

A method implemented by a status-monitoring device connected between a storage device and a corresponding output unit includes: a) determining presence of a storage device according to a first packet from the storage device; b) when it is determined that the storage device is present, generating a pulse signal according to a second packet from the storage device; c) generating a driving signal indicating a status associated with the storage device according to at least a logic level of the pulse signal; and d) sending the driving signal to the output unit for driving the output unit to output an output signal indicating the status.

Method for displaying status associated with a storage device, computer system and status-monitoring device thereof

A signal generating apparatus, for generating a power-on-reset signal, including a bias circuit and a power-on-reset signal generating circuit is disclosed. The bias circuit is for generating an output bias voltage, and includes at least one bipolar junction transistor (BJT), wherein a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT. The power-on-reset signal generating circuit is coupled to the bias circuit, and is for generating a duplicated voltage by duplicating the output bias voltage, wherein the power-on-reset signal is generated according to the duplicated voltage.

Signal generating apparatus for generating power-on-reset signal

A feedforward delta-sigma modulator includes a successive approximation analog-to-digital converter, a digital-to-analog converter, N integrators, a first adder, a second adder, and an optimization zero generation unit, where N is a positive integer. An output terminal of each integrator of the N integrators is coupled to the successive approximation analog-to-digital converter. The digital-to-analog converter is coupled between the first adder and the successive approximation analog-to-digital converter. The first adder is coupled to an input terminal of a first integrator of the N integrator. The second adder is coupled to an input terminal of a Kintegrator of the N integrators, where K is a positive integer. The optimization zero generation unit is coupled between an output terminal of a (K+1)integrator of the N integrators and the second adder.

Feedforward delta-sigma modulator

An impedance calibration device includes: a variable impedance, an operational unit, an analog-digital converter, and a controller. The operational unit receives a first analog signal and a second analog signal, and performs a difference operation to generate an output voltage. The analog-digital converter generates an adjustment code according to the output voltage. The controller is coupled to the analog-digital converter and the variable impedance, and adjusts a resistance value of the variable impedance according to the adjustment code.

Impedance calibration device and method

This algorithm provides a marker-free approach to establishing the pixel correspondence among the IR images taken at different times, which is the basis for quantitatively characterizing the variation of the heat energy and patterns pixel-wise on a breast surface. The idea is to use the corner points of the heat pattern and the branch points of the skeletons of the heat pattern on the body surface as the initial fiducial points for the longitudinal IR image registration. The Thin-Plate Spline technique is used to model the nonlinear deformation between two IR images taken at two different times. Mutual information between the TPS-transformed image and the target image is employed as the metric quantifying the quality of the longitudinal IR image registration. To optimize the registration, Nelder-Mead simplex method is used to locally modify the pairings of the fiducial points in the source and target IR images to maximize the mutual information.

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Taipei, Taiwan

Che-Wei Chang