United Microelectronics Corp.

Che-Pin Tseng

Cheng-Chih Kung

Yu-Chih Chuang

Nai-Jen Yeh

Yun-Kuei Yang

Wen-Cheng Tien

Wei-Jiang Lin

A photolithographic process which provides reduced line widths or reduced inter-element line spaces for the circuit elements on an IC chip, allowing the IC chip to have a higher degree of integration. The photolithographic process includes a double-exposure process on the same wafer defined by placing either the same photomask at two different positions or by using two photomasks. In the first exposure process, a first selected set of areas on the photoresist layer is exposed through the photomask. In the second exposure process, the photomask is shifted to predetermined positions interleaving or overlapping the positions where the first selected set of exposed areas are formed, or alternatively a second photomask replaces the first photomask. The second photomask has a plurality of patterns arranged in positions correspondingly interleaving or overlapping the positions where the first selected set of exposed areas is formed. The exposure light then illuminates the wafer again so as to expose a second selected set of areas on the photoresist layer. The first and second selected sets of exposed areas in combination constitute a layout for the circuit elements which are to be subsequently formed. Through the photolithographic process, the circuit elements are doubled in density compared with the corresponding patterns on the photomask and can be formed with a reduced line width or inter-element space.

Photolithographic process for mask programming of read-only memory

Although the spacers are formed on the sidewalls of gate electrode and words lines via the same steps of deposition and etch-back processes, only the spacers disposed at the sidewalls of the gate electrode are practical for fabricating peripheral devices with LDD structure, and such fabrication is impractical in the memory cell region. On the contrary, the region beneath the spacers disposed at the sidewalls of word lines will become the path through which leakage current flows. The present invention makes use a shielding layer to cover the second active region as a masking, and then removes the spacers disposed at the sidewalls of word lines. Afterwards, isolating regions are formed through one implantation procedure to thereby decrease leakage current and simplify the process flow.

Method for fabricating isolating regions for buried conductors

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Hsinchu, Taiwan

Che-Pin Tseng