Taiwan Semiconductor Manufacturing Comp. Ltd.

Anpec Electronics Corporation

Realtek Semiconductor Inc.

Che-Ming Hsu

Ching-Feng Fu

Yu-Lien Huang

Huan-Just Lin

Kun-Min Chen

Guan-Ren Wang

Yu-lien Huang

Yu-Hsin Wang

Nai-Jen Hsuan

Sung-Yuan Lin

A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.

Interconnect structures for semiconductor devices and methods of manufacturing the same

A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

Semiconductor device having air spacers

A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.

A method is provided for sealing a seam in a self-aligned contact (SAC) layer that is disposed on a gate of a semiconductor structure. The method includes depositing a filler in the seam to seal the seam.

Method for sealing a seam, semiconductor structure, and method for manufacturing the same

Methods of forming a semiconductor device having an air spacer

A rotation locking system of a motor of a fan is provided. A closed-loop control circuit outputs an initial duty cycle signal according to a current rotational speed and a target rotational speed. A driver circuit outputs a driving signal to the motor to drive the motor to rotate according to the initial duty cycle signal. A lookup table arithmetic circuit looks up, from a lookup table, two reference duty cycles correspond to two reference rotational speeds that are respectively equal to the current rotational speed and the target rotational speed. The lookup table arithmetic circuit calculates a difference between the two reference duty cycles. A speed feedback control circuit compensates the initial duty cycle signal according to the difference to output a final duty cycle signal to the driver circuit. The driver circuit drives the motor to rotate according to the final duty cycle signal.

Rotation locking system of motor of fan

A package substrate is adapted to a ball grid array package. The substrate includes two substrate contacts, two solder ball pads, two via holes and two signal lines. A connection line of the two substrate contacts is substantially perpendicular to a connection line of the two solder ball pads. The two substrate contacts are respectively connected to the two via holes by the two signal lines. Each signal line includes a circuit trace section, an approaching section and a bifurcating section connected in sequence. The two circuit trace sections of each signal line are substantially arranged in parallel. The two approaching sections are substantially arranged in parallel and substantially symmetrical about the connection line of the solder ball pads. The two bifurcating sections are substantially symmetrical about the pad connection line and respectively electrically connected to the two via holes.

Ball grid array package and package substrate thereof

A fan driving circuit includes a processing module providing a fan phase signal and a speed signal providing module electrically connected to the processing module and including a first switch having a first terminal, a second terminal receiving the fan phase signal and a third terminal electrically connected to a ground voltage, a second switch having a first terminal electrically connected to a speed signal providing terminal of the fan driving circuit and a first terminal of a first impedance, a second terminal electrically connected to a second terminal of the first impedance and a terminal of a diode, and a third terminal electrically connected to the first terminal of the first switch, and a third switch having a terminal electrically connected to a bias voltage.

Growing community of inventors

Hsinchu, Taiwan

Che-Ming Hsu