Texas Instruments Corporation

Che-Jen Hu

Zhiqiang (Jeff) Wu

Rajesh B Khamankar

Craig Thomas Salling

Sunil V Hattangady

Jaideep Mavoori

Haowen Bu

Seetharaman Sridhar

Antonio Luis Pacheco Rotondaro

Craig Lawrence Hall

Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.

Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement

A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.

Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process

A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.

Semiconductor with a nitrided silicon gate oxide and method

Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.

Structure and method of MOS transistor having increased substrate resistance

An integrated circuit device ( ) including a first transistor (PMOS) of a first conductivity type and a second transistor (NMOS) of a second conductivity type that is complementary to the first conductivity type. The method includes the steps of forming a first gate stack ( ), the first transistor including the first gate stack and forming a second gate stack ( ), the second transistor including the second gate stack. The method further includes implanting a first drain extension region ( ) at a first distance relative to the first gate stack, the first transistor including the first drain extension region, and the method includes implanting a second drain extension region ( ) at a second distance relative to the second gate stack, the second transistor including the second drain extension region. The first distance is greater than the second distance.

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Plano, TX, United States of America

Che-Jen Hu