Advanced Micro Devices Corporation

Other

Che-Hoo Ng

Shekhar Pramanick

Bhanwar Singh

Matthew S Buynoski

Emi Ishida

Bin Yu

Judy Xilin An

Ognjen Milic

Geoffrey Choh-Fei Yeap

Scott Allan Bell

Sunil D Mehta

Subhash Gupta

Hidehiko Shiraiwa

Pau-Ling Chen

Yue-Song He

Jean Y Yang

Yider Wu

Christopher Lee Pike

Anne E Sanderfer

Richard P Rouse

Subash Gupta

Jaime M Reyes

Balaraman Mani

Bill Chen

Shekhan Pramanick

Jinning Liu

Sandeep Mehta

The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then formed below the buried amorphous layer. The substrate is then subjected to a rapid thermal anneal to recrystallize the buried amorphous layer. The well structure is formed by the shallow well and the deep well. A conventional semiconductor device may then be formed above the well structure. The buried amorphous layer suppresses the channeling effect during the forming of the deep well without requiring a tilt angle.

Method and apparatus for suppressing the channeling effect in high energy deep well implantation

A method of increasing ion source lifetime in an ion implantation system uses the introduction of an inert gas, such as argon or xenon, into the halide-containing source gas. Inert gas constituents have a cleansing effect in the plasma ambient by enhancing sputtering.

Ion implantation with improved ion source life expectancy

The present invention relates to a system and a method for reducing the linewidth of ultra thin resist features. The present invention accomplishes this end by applying a densification process to an ultra thin resist having a thickness of less than about 2500 &angst; formed over a semiconductor structure. In one aspect of the present invention, the method includes providing a semiconductor substrate having a device film layer formed thereon. An ultra thin resist is then deposited over the device film layer. The ultra thin resist is patterned according to a desired structure or feature using conventional photolithography techniques. Following development, the ultra thin resist is implanted with a dopant. After the implantation is substantially completed, the device film layer is anisotropically etched.

Method for ultra thin resist linewidth reduction using implantation

A SOI substrate is preamorphized by ion implanting Xe prior to forming source/drain extensions and source/drain regions, thereby virtually eliminating or significantly reducing floating body effects. Other aspects comprise ion implanting a Xe into a bulk silicon or SOI substrate to effect preeamorphization prior to forming source/drain extensions and regions having shallow junctions with reduced vertical and lateral straggle.

XE preamorphizing implantation

Semiconductor devices comprising a plurality of active device regions formed in a common semiconductor substrate, e.g., CMOS devices, are formed by utilizing shallow trench isolation (STI) technology enhanced by selectively implanting the bottom surface of the trench with dopant diffusion inhibiting ions prior to filling the trench with a dielectric material and formation of opposite conductivity type well regions on either side of the trench. The inventive methodology effectively reduces or substantially eliminates deleterious counterdoping of the subsequently formed well regions resulting from thermally-induced lateral inter-diffusion of p-type and/or n-type dopant impurities used for forming the well regions.

Method of inhibiting lateral diffusion between adjacent wells by introducing carbon or fluorine ions into bottom of STI groove

A semiconductor device with reduced leakage current is obtained by forming a non-uniform channel doping profile. A high impurity region of the opposite conductive type of a source region is formed between the channel region and source region by transient enhanced diffusion (TED). The high impurity region substantially reduces the threshold voltage rolling off problem.

Non-uniform channel profile via enhanced diffusion

Contamination of semiconductor wafers are minimized during implantation processes within an implantation system. An implantation chamber of the implantation system and components within the implantation chamber are coated with additional material to minimize contaminants within the implantation chamber. For example, surfaces of the implantation chamber and/or the components of the implantation chamber are coated by performing an implantation process with a coating dopant before a semiconductor wafer is placed within the implantation chamber. In this manner, contaminants on the surfaces of the implantation chamber and/or the components within the implantation chamber are substantially coated and encapsulated with the coating dopant to prevent contact of the contaminant with the semiconductor wafer placed within the implantation chamber. Alternatively, shields are placed on surfaces of the implantation chamber and/or on surfaces of the components of the implantation chamber during an implantation process for a first semiconductor wafer having a contaminant source. Such shields are amenable for absorbing the contaminant and are removed after this implantation process and before a second semiconductor wafer is placed within the implantation chamber to minimize contamination of the second semiconductor wafer.

Minimized contamination of semiconductor wafers within an implantation system

One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a silicon substrate; a tunnel oxide layer over the silicon substrate, the tunnel oxide layer comprising fluorine atoms; a charge trapping layer over the tunnel oxide layer; an electrode or poly layer over the charge trapping layer; and source and drain regions within the silicon substrate. Another aspect of the present invention relates to a method of making a non-volatile semiconductor memory cell having improved erase speed, involving the steps of providing a silicon substrate; forming a tunnel oxide layer comprising fluorine atoms over the silicon substrate; and forming non-volatile memory cells over the tunnel oxide layer.

Flash memory erase speed by fluorine implant or fluorination

An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0&deg; to 60&deg; from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0&deg; to 60&deg; from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.

Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor

A method for determining a dosimetry of a semiconductor substrate is provided which is accurate, reliable, simple and inexpensive. The present invention is especially useful for determining dosimetry of ultra shallow junctions formed using low energy implantation commonly found in sub&minus;0.25 &mgr;m technologies. In a preferred embodiment, a material layer of a thickness is formed over a semiconductor substrate, followed by an ion implantation of a dopant. The material layer is then analyzed using a chemical method such as vapor phase plasma deposition inductively coupled plasma mass spectroscopy with atomic absorption (VPD-ICPMS-AA) to determine the amount of dopant present in the material layer.

Method for determining ultra shallow junction dosimetry

Chemical mechanical polishing for removing a hardened surface layer of photoresist in the manufacture of semiconductor devices. The use of chemical mechanical polishing allows for the removal of a hardened surface layer of photoresist that has been hardened through ion beam implantation or plasma etching. The chemical mechanical polishing process places a semiconductor wafer with a photoresist layer on a polishing pad. The photoresist layer is placed close to the polishing pad, so that the hardened surface layer of the photoresist layer is removed. A slurry is added to the polishing pad to aid in the removal of the hardened surface layer of the photoresist layer. Conventional chemical stripping is then used to remove the remaining photoresist layer.

Resist removal by polishing

A method of preparing a narrow photoresist line by first forming a resist pattern on a substrate, wherein a resist line is designed to have a width &ldquo;w&rdquo; in excess of a desired width &ldquo;w,&rdquo; The resist is then subjected to ionic bombardment with ionized particles in a direction normal to the planar surface of a resistant substrate. The ionic bombardment causes formation of a hardened &ldquo;chemically less reactive&rdquo; skin on the exposed top surface of the photoresist. The resist is then subjected to an isotropic etch procedure. Due to the hardened top surface of the narrow pattern, the side wall erode at a faster rate than the top, causing a narrowing of the line width, while retaining a more substantial photoresist thickness than would occur if the top surface would not be hardened in advance of the etch procedure.

Method for preparing narrow photoresist lines

Semiconductor with laterally non-uniform channel doping profile

A method for forming a shallow junction in a semiconductor device includes the steps of ion implanting a molecular antimony dimer (Sb,&plus;) into a semiconductor substrate. The antimony dimer implantation process creates a shallow doped junction having a high dopant concentration and a shallow junction depth. The antimony dimer ion is extracted from an antimony source material at an extremely low extraction voltage. The use of a low extraction voltage enables the antimony dimer ion to be analyzed by an analyzer magnetic within the ion implantation device. The process of the invention can be used to form a variety of shallow dope structures in semiconductor devices, such as source/drain extension regions, implanted resistors, and the like.

Growing community of inventors

San Martin, CA, United States of America

Che-Hoo Ng