Mediatek Corporation

National Taiwan University

Industrial Technology Research Institute

Mediatek Singapore Pte. Ltd.

Che-Fu Liang

Sy-Chyuan Hwu

Shen-Iuan Liu

Shen-luan Liu

Michael Anthony Ashburn, Jr

Gin-Kou Ma

Tzu-Yi Yang

Keng-Jan Hsiao

Yu-Hsuan Tu

Tsung-Kai Kao

Hsin-Hua Chen

Michael A Ashburn Jr

A loop filter has a first switched-capacitor network and a second switched-capacitor network. The first switched-capacitor network is coupled to an input node of the loop filter. The second switched-capacitor network is coupled to the input node of the loop filter. The input node of the loop filter is arranged to receive an input from a charge pump.

Switched-capacitor loop filter

A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.

Segmented fractional-N PLL

An injection-locked phase-locked loop (ILPLL) with a self-aligned injection window is disclosed. In the ILPLL, a phase detector is provided to detect a phase difference between a pair of differential terminals of an injection-locked voltage-controlled oscillator (ILVCO) of the ILPLL. According to the detection, the phase detector generates a control signal, to align an oscillation output, generated from the pair of differential terminals of the ILVCO, with an injection pulse utilized in the ILVCO.

Injection-locked phase-locked loop with a self-aligned injection window

An oscillator circuit is provided. The oscillator circuit includes a gated oscillator and a calibration circuit. The gated oscillator is arranged to generate an oscillator signal according to a control signal, and receive a gating signal to align an edge of the oscillator signal with an edge of the gating signal. The calibration circuit coupled to the gated oscillator is arranged to receive a first clock signal and a second clock signal, detect an alignment operation of the gated oscillator according to the first clock signal and a second clock signal and generate the control signal according to the detected alignment operation.

Methods for calibrating gated oscillator and oscillator circuit utilizing the same

A clock and data recovery circuit is disclosed and comprises a gated voltage-controlled oscillator (GVCO), a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop (DDFF). The GVCO receives a data signal and a reference voltage to generate first and second clock signals. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the first and second clock signals at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The DDFF receives the output signals from the matching circuit and the multiplexer, and outputs a recovered data signal.

Multi-band burst-mode clock and data recovery circuit

An embodiment of a clock and data recovery circuit comprising a first clock and data recovery circuit with high bandwidth and a second clock and data recovery circuit with low bandwidth is disclosed. The first clock and data recovery circuit with high bandwidth receives a data signal and a reference signal to demux the data signal into a first signal and a second signal, wherein a second data rate X bps of the first signal and the second signal is half of a first data rate of the data signal. The second clock and data recovery circuit with low bandwidth receives and reduces jitter in the first signal and the second signal to output a first recovery signal and a second recovery signal.

Jitter-tolerance-enhanced CDR using a GDCO-based phase detector

A frequency synthesizer for generating a plurality of frequencies of a MB-OFDM UWB system is disclosed, wherein the frequencies include first to fourteenth frequencies from low to high and any of the adjacent two frequencies differs by a basic intervallic frequency. The frequency synthesizer includes a phase locked loop generating an initial signal with a frequency equal to the second frequency, an intervallic frequency generator generating first to third intervallic frequencies from low to high and all being integers times the basic intervallic frequency and generating a forth intervallic frequency equal to the basic intervallic frequency, and first to third mixers connected in series, respectively receiving the fourth intervallic frequency, one of the first to third intervallic, and the first intervallic frequency, to respectively generate the first to third frequencies, the fourth to ninth and the thirteenth to fourteenth frequencies, and the tenth to twelfth frequencies.

Frequency synthesizer and frequency synthesizing method

A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay.

Growing community of inventors

Taipei County, Taiwan

Che-Fu Liang