Interdigital Technology Corporation

Chayil S Timmerman

Ryan Samuel Buchert

Tonino Nasuti

Peter Edward Becker

Stephan Shane Supplee

Muhammad U Fazili

John W Haim

Robert A DiFazio

Younglok Kim

Ryan S Buchert

A method and apparatus perform many different types of algorithms that utilizes a calculation unit capable of utilizing the same multipliers for different algorithms. The calculation unit preferably includes a processor that has a plural number of arithmetic logic unit circuits that are configured to process data in parallel to provide processed data outputs and an adder tree configured to add the processed data outputs from the arithmetic logic circuits. A shift register that has more parallel data outputs then the processor's inputs is controlled to selectively output data from the parallel outputs to the data inputs of the processor. A communication device preferably includes the calculation unit to facilitate processing of wireless communication signals.

Computationally efficient mathematical engine

Method and apparatus for performing midamble cancellation to remove midamble interference from the convolution tail of data fieldand the first W&#x2212;1 chips of the midamble field which results from the delay spread of the multipath channel and for canceling the first W&#x2212;1 chip midamble spread in the data field, which operations are performed substantially simultaneously. The received burst, typically a TDD burst, is stored, the midamble interference and the corresponding parts in the received burst is removed and the resulting burst is applied to a multi-user detector to obtain the symbol sequences.

Method and apparatus for parallel midamble cancellation

Method and apparatus for performing midamble cancellation to remove midamble interference from the convolution tail of data fieldand the first W-1 chips of the midamble field which results from the delay spread of the multipath channel and for canceling the first W-1 chip midamble spread in the data field, which operations are performed substantially simultaneously. The received burst, typically a TDD burst, is stored, the midamble interference and the corresponding parts in the received burst is removed and the resulting burst is applied to a multi-user detector to obtain the symbol sequences.

A hermetian of a system response matrix is to be determined. Spreading codes, channel specific multipliers and channel impulse responses are provided. The channel code specific multipliers have real and imaginary values. Channel codes being a combination of a real spreading code, a complex scrambling code and a sign of the channel code specific multiplier. Real and imaginary components of an approximate hermetian of the system response matrix are determined. The channel code specific multipliers are applied to the real and imaginary components of a result of the convolutions to derive the hermetian of the system response matrix.

CDMA system transmission matrix coefficient calculation

A method and system for performing many different types if algorithms utilizes a single mathematical engine such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical engine includes a selectively controlled parallel output register, at least one selectively controlled memory, and a plurality of processing elements. The output register, the memory and the processing elements are selectively controlled depending upon the algorithm to be performed.

Method and apparatus for performing midamble cancellation to remove midamble interference from the convolution tail of data field 1 and the first W-1 chips of the midamble field which results from the delay spread of the multipath channel and for canceling the first W-1 chip midamble spread in the data field 2, which operations are performed substantially simultaneously. The received burst, typically a TDD burst, is stored, the midamble interference and the corresponding parts in the received burst is removed and the resulting burst is applied to a multi-user detector to obtain the symbol sequences.

An insertion sorter circuit and method are provided which are particularly useful for sorting channel response values of a communication signal. The sorter circuit includes a series of sorter elements which each have a register. The circuit is configured to cascade values downwardly when one register receives a greater value than it has stored, which value is not greater than the value stored in any upstream register. At the end of processing the values, the most significant values are stored in the registers, the sum of which are the channel power estimate. The channel noise variance is obtainable by applying a system dependent scaling factor to the sum of the least significant values processed.

Insertion sorter

Multi-user detection (MUD) performance is optimized to eliminate redundant use of power during processing. An overbuilt A-matrix, i.e., a system response matrix, is provided. The overbuilt A-matrix uses all possible codes, e.g., all codes identified in a candidate code list (CCL) provided by blind code detection (BCD). The overbuilt A-matrix is passed to the MUD which extracts only those rows or columns required for codes that have actually been received, thus eliminating the need to recompute whitening matched filter (WMF) outputs that do not correspond to the actually received code.

Wireless communication method and apparatus for optimizing multi-user detection

An apparatus and method for data processing particularly useful in combining convolutions of the spreading code, scrambling code and channel response in order to construct a system transmission coefficient matrix, while maintaining the same circuit size and execution time relative to performing each convolution separately. One register for processing real channel response values and a second register for processing imaginary channel response values, are used for moving channel responses through the convolution. In place of multipliers, an optimized minimum number of adders connected in a pyramid configuration are used to perform the necessary multiplication of the codes, for simplicity of construction. By including the channel code transformation from binary representation to complex representation as part of the overall method, unnecessary adders are eliminated from the apparatus.

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Harleysville, PA, United States of America

Chayil S Timmerman