Texas Instruments Corporation

Chauncey L Everett

Theodore Warren Houston

Henry M Darley

A noninverting amplifier circuit for one propagation delay complex logic gates. The noninverting amplifier circuit is compatible with field effect transistor logic, including depletion-mode Schottky barrier field effect transistor (MESFET) inverting logic, gates. The basic noninverting amplifier circuit, utilizes field effect transistors (FET) and diodes, and comprises input interface means for receiving an input voltage signal, amplifier means for providing noninverted amplification of the input voltage signal, and buffer means for driving, and shifting the voltage level of the amplified input voltage signal. In another embodiment, additional circuit means for enabling performance of the 'AND' logic function is included in the basic noninverting amplifier circuit. In a third embodiment, additional circuit means for enabling performance of the 'OR' logic function is included in the basic noninverting amplifier circuit. The input and output voltages of the various embodiments which utilize the noninverting amplifier logic circuit are compatible with those of inverting logic circuits. Some examples of higher level complex one propagation delay logic gates which utilize the circuit in combination with inverting logic circuitry are also illustrated.

Noninverting amplifier circuit for one propagation delay complex logic

A static-type noninverting memory cell for one propagation delay memory circuits which is compatible with inverting and noninverting field effect transistor logic, such as, for example, depletion mode Schottky barrier field effect transistor (MESFET) inverting logic. The basic memory cell utilizes field effect transistors and a diode, and comprises an input for receiving an input signal, a transistor operating in a switching mode and connected to the input for registering the logic state of the input signal, a memory section which includes a pair of transistors each of whose respective gates are connected to the sources, a diode interposed therebetween, and a logic state-holding transistor for retaining a stored logic state of the registered input signal, and an output terminal connected between the diode and one of the transistor pair of the memory section from which the stored logic state within the memory section may be sensed. In one embodiment, the basic memory cell is combined with noninverting logic gates to provide a one propagation delay D type flip-flop memory circuit. In another embodiment, the basic memory cell is combined with noninverting logic gates to provide a one propagation delay D bar type flip-flop memory circuit. The input and output voltages of the various embodiments of the subject invention are compatible with those of inverting and noninverting logic circuits.

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Richardson, TX, United States of America

Chauncey L Everett