Motorola Corporation

International Business Machines Corporation

Chau-Shing Hui

Barry Joe Wolford

John D Coddington

Krishnamurthy Venkatramani

A system (,) has a shifting delay circuit (,) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (,) which includes a delay line (,) which provides a variable delay for delaying the source clock. The delay line (,) has its delay varied by a counter (,). The counter (,) is incremented in order to change the delay. The shifting delay circuit (,) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (,) and delay line (,). The delay line (,), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (,).

System with DLL

A method of providing a value to a cache used in a computer system, by transmitting the value from a system memory device to a lower level (e.g., L2) of the cache using a system bus, acknowledging the forwarding of the address from the lower level of the cache after said transmitting of the value, and acknowledging the forwarding of the address from a higher level (e.g., on-board) of the cache, in response to said transmitting step. The acknowledging of the forwarding of the address from the higher level of the cache, can occur prior to the acknowledgment of the forwarding of the address from the lower level of the cache. The value is transmitted from the lower level of the cache to the higher level of the cache using the higher level bus, in response to said acknowledgement of the forwarding of the address from the higher level of the cache, and this latter transmission can also occur prior to said acknowledgment of the forwarding of the address from the lower level of the cache. This approach results in reduced memory access latency with L2 cache misses, and improves address bus utilization on the higher level bus.

Method and apparatus to reduce system bus latency on a cache miss with address acknowledgments

A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).

A method of avoiding contention on a communications bus using an improved tri-state driver, which negates one of the internal driver signals during a restore region of the driver cycle, such that the driver cannot switch to the high state when there is poor synchronization that delays one of the internal driver signals. Restoring logic provides a first logic signal and a second logic signal. An input gate is asserted to an active level in response to the first logic signal, and gating logic conditionally enables the input gate in response to the second signal.

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Austin, TX, United States of America

Chau-Shing Hui