Winbond Electronics Corporation

Windbond Electronics Corp.

Chau-Neng Wu

Ta-Lee Yu

Ming-Dou Ker

Chung-Yu Wu

Chien-Chang Huang

Chi-Hsi Wu

Shi-Tron Lin

Alex Wang

Konrad Kwang-Leei Young

Ling-Yen Yeh

Ming-Tsan Yeh

Frank S-t Lin

Tao Cheng

A capacitor-triggered electrostatic discharge (ESD) protection circuit is disposed between a metal pad and V.sub.ss potential level, wherein the pad may be an input pad, an output pad, or a V.sub.DD power rail. The circuit includes a thick oxide device, a capacitor, and a resistor. The thick oxide device is configured with its drain and source connected to the pad and circuit ground V.sub.SS, respectively. The gate of the thick oxide device is tied to the pad, and the oxide device bulk is coupled by the resistor to circuit ground V.sub.SS. The capacitor is connected between the pad and the bulk of the thick oxide device. The bulk of the device is constructed by a P-well region formed in a substrate. The capacitor is formed between the pad and a polysilicon layer just therebelow, without consuming extra layout areas. When a positive-to-ground ESD pulse is conducted at the pad, the capacitor will couple the ESD voltage to the well region, forward bias the bulk/source junction, and then turn on the thick oxide device operated in a bipolar mode to bypass the ESD stress. Moreover, a diode is connected between the pad and circuit ground by its cathode and anode, respectively, to bypass a negative-to-ground ESD pulse. The diode can be an extra or built-in PN junction.

Capacitor-triggered electrostatic discharge protection circuit

An electrostatic discharge protection circuit formed in a semiconductor substrate includes a vertical bipolar junction transistor having a base which is grounded, an emitter connected to an output/input bonding pad of an integrated circuit, and a collector connected to a high power source via a resistor. The resistor is a parasitic resistor created by controlling the distance between the diffusion regions or the distance between a p-type well region and an n-type well region or formed by a lightly doped diffusion region in the semiconductor substrate to prevent current crowding and increase electrostatic protection.

Electrostatic discharge protection circuit

A CMOS device containing a plurality of hexagon cells over a semiconductor substrate is disclosed. Each hexagon cell includes a hexagonal ring gate, a drain diffusion region and a source diffusion region. The hexagonal ring gate is made of conducting materials and a dielectric layer over the substrate, therefore defining a channel region in the substrate between the gate and the substrate. The entire drain diffusion region in the substrate is enclosed by the hexagonal ring gate. The source diffusion region surrounds the hexagonal ring gate in the substrate. Each hexagon cell further provides a drain contact in the center of the drain diffusion region. A plurality of source contacts are arranged around the ring gate over the substrate. The hexagon cells of a unique hexagon device are surrounded by a first guard ring and a second guard ring. The hexagon device can be used as a CMOS output buffer or input ESD protection circuit to reduce the layout area of an integrated circuit.

Hexagon CMOS device

A bit-line pull-up circuit for an SRAM device which utilizes an improved diffusion structure for enhanced immunity of the SRAM device against electrostatic discharge. The improved diffusion structure includes an undivided diffusion region that serves as a common drain for a plurality of MOS transistors. The undivided diffusion region has at least a pair of recessed diffusion edges formed on opposite sides thereof. The forming of the recessed diffusion edges prevents the so-called electrical field crowding effect and also enhances ESD immunity for the MOS transistor. Further, since the drain diffusion region is an undivided area, an increased number of metal contact windows are provided therein, and at least one of the metal contact windows is arranged substantially between the two recessed diffusion edges. In the event of an electrostatic discharge, this allows the discharge current flowing into the drain to be divided into a greater number of small-magnitude currents flowing to the source.

Bit-line pull-up circuit or static random access memory (SRAM) devices

An electrostatic discharge (ESD) protection device includes a drain region and a source region, each having a heavily-doped region and a lightly-doped region, wherein the junction depth of the lightly-doped region is deeper than that of the heavily doped region. Accordingly, the ESD current density will be decreased owing to the enlarged junction area during the ESD event. In addition, the heat dissipation can be spread over the enlarged junction area instead of being focused on the drain cylindrical edge. Moreover, low parasitic capacitance in the bond pad is achieved because the junction capacitance of the lightly-doped region is smaller than that of the heavily-doped region. Furthermore, conducting blocks are arranged between the lightly-doped regions and the source/drain electrodes, respectively, to prevent the metal melt filament from spiking the junction.

Electrostatic discharge protection device and its method of fabrication

An electrostatic discharge protection network which diverts ESD stress arising between any two contact pads of an IC device, in order to prevent damage to the internal circuitry of the IC device. An ESD discharge bus is arranged around the periphery of an IC chip. Between each IC pad and the discharge bus, there is a protection circuit to directly bypass an ESD stress arising at any two IC pads. Each ESD protection circuit includes a diode, a thick-oxide device, a resistor, and a capacitor. The protection circuit is operated in snapback mode without causing breakdown. Therefore, the triggering voltage of the ESD protection circuit is lowered to the level of the snapback voltage but not to the level of the breakdown voltage.

Electrostatc discharge protection network

The present invention is an electronic device, and more particularly an MOS transistor. A square-type layout style is used to realize the MOS device. By using the present layout style, the output driving/sinking capability of output buffers as well as the ESD protection capability of NMOS and PMOS devices in output buffers or input ESD protection circuits are significantly improved within smaller layout area. Both drain diffusion area and drain-to-bulk parasitic capacitance at the output node are reduced by this square-type layout. Devices using the present layout style can be assembled to form larger, rectangular (or square) and similarly functioning devices. Thus, the present square-type layout style is very attractive to submicron CMOS VLSI/ULSI in high-density and high-speed applications.

Electrostatic discharge protection device

An electrostatic discharge (ESD) protection circuit connected to an integrated circuit pad for protecting an internal circuit from ESD damage. The ESD protection circuit includes an NMOS/PMOS transistor, a capacitor, and a load. The NMOS/PMOS is configured with a drain connected to the IC pad and a source for connection to the circuit V.sub.SS /V.sub.DD. A gate of the NMOS/PMOS transistor is tied to the source. The capacitor is connected between the IC pad and the bulk of the NMOS/PMOS transistor. The load, which is either another NMOS/PMOS transistor or a resistor, is to be connected between the V.sub.SS /V.sub.DD and the bulk of the NMOS/PMOS transistor. In accordance with the invention, the NMOS/PMOS transistor is fabricated in a P-well/N-well region of a semiconductor substrate. The capacitor includes an IC pad and a polysilicon layer therebelow, with an intervening dielectric layer.

Electrostatic discharge protection circuit triggered by

An electrostatic discharge (ESD) protection circuit is disposed between a metal pad and a circuit ground, wherein the pad may be an input pad or an output pad. The circuit includes a thick oxide device, a capacitor, and an NMOS transistor. The thick oxide device is configured with its drain and source connected to the pad and circuit ground, respectively. The gate of the thick oxide device is tied to the pad, and the oxide device bulk is connected to the drain of the NMOS transistor. The NMOS transistor is configured with its source connected to the circuit ground and its gate controlled by a power rail. The capacitor is connected between the pad and the bulk of the thick oxide device. The bulk of the device is constructed by a P-well region formed in a substrate. The capacitor is formed between the pad and a polysilicon layer just therebelow, without consuming extra layout area. When a positive-to-ground ESD pulse is conducted to the pad, the capacitor couples the ESD voltage to the well region and turns on the thick oxide device to bypass the ESD stress. Moreover, a diode is connected between the pad and circuit ground by its cathode and anode, respectively, to bypass a negative-to-ground ESD pulse. The diode can be an extra component or a built-in PN junction. In normal operation, the NMOS transistor is powered on and connects the bulk of the device to the circuit ground without floating of the P-well region.

Electrostatic discharge protection circuit triggered by well-coupling

The present invention is related to a capacitor-couple electrostatic discharge (ESD) protection circuit for protecting an internal circuit and/or an output buffer of an IC from being damaged by an ESD current. The capacitor-couple ESD protection circuit according to the present invention includes an ESD bypass device for bypassing the ESD current, a capacitor-couple circuit for coupling a portion of voltage to the ESD bypass device, and a potential leveling device for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the present ESD protection circuit, the snapback breakdown voltage can be lowered to protect the very thin gate oxide of the internal circuit especially in the submicron CMOS technologies.

Growing community of inventors

Kaohsiung Hsien, Taiwan

Chau-Neng Wu