Industrial Technology Research Institute

Chau-Kai Hsieh

Jeng-Yih Wang

A stand-alone, real-time voice recognition system, which converts an analog voice signal into serial digital signal, then preprocesses in parallel the digital signal to detect the end-point, and output fixed multi-order prediction coefficients. In this recognition system, these multi-order prediction coefficients are stored as the reference pattern in the training mode. In recognition mode, these multi-order prediction coefficients are adapted by dynamic time warping method, which is modified by a symmetric form. This symmetric form is implemented with a one-dimensional circular buffer for dynamic programming matching instead of the traditional two-dimensional buffer to save memory space. Finally, these adapted coefficients are compared with reference pattern to output the result of recognition.

Endpoint detection in a stand-alone real-time voice recognition system

The present invention comprises an interpolation circuit for performing a linear interpolation operation for a voice synthesizer receiving a plurality of frames of voice data wherein each frame is subdivided into a plurality of sub frames with each sub frame being assigned with a predefined interpolation weighting factor. The interpolation circuit comprises an input port for receiving a plurality of sub frame voice data to be interpolated wherein said sub frame data are received in a predefined order. The interpolation circuit further includes a read-only-memory (ROM) for storing a plurality of multiplications of each of the plurality of sub frame voice data to each of the weighting factors and a read-only-memory (ROM) address generator capable of determining a address in ROM utilizing the sub frame voice data received from the input port and the predefined order of the frame and the sub frame thereof when the voice data is being received. The interpolation circuit further includes an output means for reading a multiplication from the ROM at the address and sequentially adding each of the multiplications to compute an interpolation value.

System architecture and method for linear interpolation implementation

A digital speech encoder and decoder have particular application to the field of 16 kbps digital communications. In the encoder, a speech signal is processed by a perceptual weighting filter, using a reconstructed speech signal, a reconstructed residual signal, and a set of filter tuning coefficients. A predictive signal, which is generated by a Short Term Predictive (STP) circuit, is subtracted from the signal outputted from the perceptual weighting filter. The difference signal is processed by a coder/decoder circuit to produce a reconstructed error signal, which is added to the predictive signal to form the reconstructed residual signal. A Linear Predictive Coding (LPC) circuit receives the reconstructed residual signal and develops the set of filter tuning coefficients. The set of filter tuning coefficients are outputted to the STP circuit, which also receives the reconstructed residual signal, and thereby generates the predictive signal. The set of filter tuning coefficients are also outputted to the perceptual weighting filter, and to a complementary inverse perceptual weighting filter. The inverse perceptual weighting filter also receives the reconstructed residual signal, in accordance with the set of filter tuning coefficients. The decoder includes identical STP, LPC, and inverse perceptual weighting filter circuits for reconstructing the received signals from the encoder.

Low delay, middle bit rate speech coder

A baby cry recognizer is disclosed which includes an amplifier circuit for amplifying a received sound signal. In response to the amplified sound signal, a pulse generator circuit generates a pulse signal having zero crossings which are aligned with zero crossings of the amplified sound signal. The pulse signal, in turn, is inputted to a signal recognition circuit. The signal recognition circuit is capable of obtaining the zero crossing rate of the pulse signal during each of a preselected number of frames in a predetermined length time interval. The signal recognition circuit then determines if the zero crossing rate of the pulse signal, in more than a first threshold number of this preselected number of frames, is within a particular frequency range. The signal recognition circuit also determines if the zero crossing rate of the pulse signal over the entire time interval is greater than or equal to a second low threshold but less than or equal to a third high threshold. If these two conditions are satisfied, then the signal recognition circuit outputs a signal indicating that a baby's cry was detected.

Growing community of inventors

Hsinchu, Taiwan

Chau-Kai Hsieh