Holtek Microelectronics Inc.

Utek Semiconductor Corporation

Chau-Her Lu

A digital data separator for separating data signals from clock signals contained in an encoded data stream in alternating data/clock slots without requiring a phase-locked loop. The digital data separator comprises: (a) a system clock source for generating system clock pulses; (b) an up-counter coupled to the system clock source for incrementing a system clock count, the up-counter is structured such that the system clock count is incremented by the system clock pulses and is reset to zero upon receiving a reset signal; (c) a state generator containing an edge detector for detecting an edge transition in an input signal within a predetermined range of system clock counts, and a combination logic for generating a data control signal, a reference clock control signal, and the reset signal when such edge transition in the input signal is detected within the predetermined range of system clock counts or when the system clock counts reaches a predetermined value; and (d) a window and data generator for generating regenerated clock and data signals in response to the data control signal and the reference clock control signal received from the state generator.

Digital data separator for separating data signals from clock signals in

A digital phase-locked loop locks to the reference clock signal in the encoded input data stream and separates the reference clock signal from the actual data signal. The digital phase-locked loop includes a digital oscillator that generates a pulse train with a period continuously adjusted in accordance with time variations in the input data stream so as to maintain the regenerated data in proper phase relationship with the reference clock. The digital phase-locked loop also contains a predict phase generator that generates a predict phase with a fraction part in order to improve the precision of phase adjustment without increasing frequency of the system clock. The circuit also includes a digital low pass filter that generates a first order predict phase, of which the small transient phase variation in the reference clock is removed such that the frequency stability of the recovered reference clock is enhanced. The data window and data regenerator of the circuit generates the data window signal to help separation of reference clock from actual data and regenerated data signal that is more evenly spread in time and more stable in frequency.

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Tainan, Taiwan

Chau-Her Lu