Texas Instruments Corporation

Hewlett-packard Company

University of Illinois

Esd It2 Llc.

Charvaka Duvvury

Gianluca Boselli

Chih-Ming Hung

Sridhar Ramaswamy

Carlos H Diaz

Michael D Chaine

Keith Edmund Kunz

Roger A Cline

Adin E Hyslop

Sung-Mo Steve Kang

Amitava Chatterjee

Fernando D Carvajal

Robert N Rountree

John Eric Kunz, Jr

David D Briggs

Craig Thomas Salling

Hisashi Shichijo

Roy Clifton Jones, Iii

Dan M Mosher

E Ajith Amerasekera

Steven E Marum

Kyle Clifton Schulmeyer

Ekanayake Ajith Amerasekera

Kwang-Hoon Oh

Ponnarith Pok

Puvvada Venugopal

Tatsuroh Maki

Baher S Haroun

Kurt Peter Wachtler

Bernhard H Andresen

Robert Steinhoff

Heng-Chih Lin

Thomas A Vrotsos

Larry Baoqi Li

Snehamay Sinha

Ismail Hakki Oguzman

Julian Zhiliang Chen

Yves Leduc

Ping Yang

Amjad Hussain

Janet L Wise

Nathalie Messina

Guru Chakrapani Prasad

Jorge Salcedo-Suner

C S Raghu

Gopalaro Kadamati

Stephane Bertonnaud

Michael O Chaine

Svetlana Loshakov

Fred Carvajal

Russel W Strawn

Jose A Cadena-Hernandez

A method for electrostatic discharge (ESD) testing and analysis includes performing, by an ESD testing device, ESD testing on pins of an integrated circuit (IC) device to generate pre-stress ESD test data for each of the pins and post-stress ESD test data for each of the pins, determining, current shifts according to first data points of voltage-current (IV) curves of the pre-stress ESD test data corresponding to the IC device pins and to second data points of IV curves of the post-stress ESD test data corresponding to the respective pins of the IC device, assigning, by the device, a test result classification for each of the pins according to a relationship between a test threshold and the current shift for the respective pin, and displaying, by a workstation, a visually coded map of the IC device indicating the test result classification for each of the pins.

System and method for efficient electrostatic discharge testing and analysis

An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

ESD protection using diode-isolated gate-grounded nMOS with diode string

ESD protection using diode-isolated gate-grounded NMOS with diode string

An electronic system protected against an incoming energy pulse, comprising a semiconductor device () connected in sequential order to a first impedance (), a coupling noise filter () having an internal frequency-dependent second impedance (), a third impedance (), a transient voltage suppressor (), a fourth impedance (), and an entry port exposed to the incoming energy pulse (). The fourth impedance has a size suitable for supporting the transient voltage suppressor in discharging a portion of the incoming energy pulse up to the full capability of the suppressor; the third impedance has a size suitable for supporting and synchronizing the performance of the coupling noise filter to filter common mode noise from two phase lags between differential signals; and the first impedance has a size suitable for diminishing, in combination with the second impedance as operational in the active frequency regime, the un-discharged portion of the energy pulse to a value under the device threshold failure current.

ESD protection system optimized at board level

An integrated circuit () formed at a semiconducting surface of a substrate including a common p-layer () includes functional circuitry () formed on the p-layer () including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (). At least one ESD protection cell (in more detail) is connected to at least one of the plurality of terminals of the functional circuitry (). The protection cell includes at least a first Nwell () formed in the p-layer (), a p-doped diffusion () within the first Nwell () to form at least one Nwell diode comprising an anode () and a cathode (). An NMOS transistoris formed in or on the p-layer () comprising a n+ source (), n+ drain () and a channel region comprising a p-region () between the source and drain, and a gate electrode () on a gate dielectric () on the channel region. The terminal of the functional circuit (, PAD) is coupled to the cathode () of the Nwell diode, and the anode () of the Nwell diode is connected in series with a path from the drain () to the source () of the NMOS transistor ().

MOS device with substrate potential elevation for ESD protection

A packaged semiconductor device () with a substrate () having, sandwiched in an insulator (), a flat sheet-like sieve member () made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set () and a second set (). Metal traces () over one member surface are positioned across the first set through-holes (); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces () over the opposite member surface and second set through-holes (). Traces () overlap with a portion of traces () to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.

In package ESD protections of IC using a thin film polymer

An ESD protection circuit () is guarded by a parallel first precharge elimination circuit () relative to an I/O pad () and a parallel second precharge elimination circuit () relative to a VDD pad (). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode () is connected between I/O pad and VDD. Circuit () is between I/O pad and ground () and is powered by the same VDD. Circuit () includes a first resistor (), a first nMOS transistor (), and a first RC timer including a second resistor () and a first capacitor (). Circuit () includes a third resistor (), a second nMOS transistor (), and a second RC timer including a fourth resistor () and a second capacitor ().

Methodology to guard ESD protection circuits against precharge effects

An integrated circuit () formed at a semiconducting surface of a substrate including a common p-layer () includes functional circuitry () formed on the p-layer () including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (). At least one ESD protection cell (; in more detail) is connected to at least one of the plurality of terminals of the functional circuitry (). The protection cell includes at least a first Nwell () formed in the p-layer (), a p-doped diffusion () within the first Nwell () to form at least one Nwell diode comprising an anode () and a cathode (). An NMOS transistoris formed in or on the p-layer () comprising a n+ source (), n+drain () and a channel region comprising a p-region () between the source and drain, and a gate electrode () on a gate dielectric () on the channel region. The terminal of the functional circuit (, PAD) is coupled to the cathode () of the Nwell diode, and the anode () of the Nwell diode is connected in series with a path from the drain () to the source () of the NMOS transistor ().

MOS device with substrate potential elevation

A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad () against ESD events, when the I/O pad is located between a power pad () and a ground potential pad (). A first diode () and a second diode () are connected in series, the anode () of the series connected to the I/O pad and the cathode () connected to the power pad. A third diode () has its anode () tied to the ground pad and its cathode () tied to the I/O pad. A string () of at least one diode has its anode () connected to the series between the first and second diode (node), isolated from the I/O pad, and its cathode () connected to the ground pad. The string () may comprise three or more diodes.

Local ESD protection for low-capicitance applications

An ESD protection circuit is designed on an integrated circuit () having a first power supply bus () and a second power supply bus (). The circuit includes a first logic gate () having a current path coupled to the first power supply bus. The first logic gate includes an output terminal. A second logic gate () has a current path coupled to the second power supply bus. The second logic gate has an input terminal coupled to the output terminal of the first logic gate. A first device () is coupled in series with the current path of the second logic gate and is always on during normal circuit operation.

Circuit to reduce internal ESD stress on device having multiple power supply domains

A semiconductor dual guardring arrangement is provided which is useful during electrostatic discharge (ESD) events as well as during normal operating conditions. In particular, an inner guard that is located closer to an active area provides desirable performance during normal operating conditions, while an outer guardring located further from the active area provides desirable performance during an ESD event.

Semiconductor dual guardring arrangement

A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor () in a first n-well () having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact () to the first n-well, which touches source junction. Sourcehas further an ohmic (silicided) connection to contact. A finger-shaped diode () with its cathode () is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well () positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall ().

Guardwall structures for ESD protection

An electrostatic discharge (ESD) device for protecting a power amplifier circuit is disclosed. The ESD device comprises a first ESD protection circuit coupled between a positive terminal of a supply voltage and a negative terminal of the supply voltage, and a second ESD protection circuit coupled between the negative terminal of the supply voltage and an output terminal of the power amplifier circuit, wherein a first current path is formed from the positive terminal to the output terminal through the first and second ESD protection circuits. A circuit device operative to increase impedance of a second current path from the positive terminal to the output terminal through the power amplifier circuit to divert current from the second current path to the first current path in the course of an ESD event.

ESD protection for RF power amplifier circuits

Local ESD protection for low-capacitance applications

Growing community of inventors

Plano, TX, United States of America

Charvaka Duvvury