Lsi Logic Corporation

Charutosh Dixit

Prasad Subbarao

Bo Shen

Alexander Y Tetelbaum

Sandeep Bhutani

William Shen

Radoslav Ratchkov

Thomas Mathews Antisseril

Julie Beatty

Prabhakaran Krishnamurthy

Qiong J Yu

Subramanian Venkateswaran

Soon-lin Yeap

A method and system of testing data retention of memory is provided. An embodiment of the method of testing data retention of memory comprises: writing first data to a first memory sub-group during a first time period; writing second data to a second memory sub-group during a second time period subsequent to said first time period; pausing for a predetermined time interval during a third time period subsequent to said second time period; reading a first one of said first and second data during a fourth time period subsequent to said third time period; reading a second one of said first and second data during a fifth time period subsequent to said fourth time period; and comparing said first and second ones of read data to expected results to determine data retention capabilities of said first and second memory sub-groups.

Method and system of testing data retention of memory

A method for modeling the output waveform of a cell driving a resistance-capacitance network includes multiple effective capacitances. A method of calculating Thevenin parameters includes the steps of (a) initializing estimates of effective capacitances Ceff1 and Ceff2, of a switching threshold delay t0, and of a slope delay deltat; (b) solving ramp response equations for t0 and deltat as a function of Ceff1 and Ceff2; (c) comparing the estimates of t0 and deltat with solutions for t0 and deltat found in step (b); and (d) replacing the estimates of t0 and deltat with the solutions for t0 and deltat if the solutions for t0 and deltat have not converged to the estimates of t0 and deltat.

Driver waveform modeling with multiple effective capacitances

A method for checking power errors in an ASIC design is disclosed. The method includes providing a power checker software program with one or more power checker modules that each check a particular type of power element in the ASIC design. A power checker database is created that stores the following: individual power elements in the ASIC design, a connectivity graph of the power elements, and location bins corresponding to physical areas in ASIC design that identify the power elements that are located within each area. The method further includes providing a user with a choice of which power elements in the design to check, and executing the power checker modules corresponding to the selected power elements in order to check for errors in the selected power elements. Finally, any detected errors are output for the user.

Method and system for checking for power errors in ASIC designs

Methods for calculating a total capacitance of a metal wire in an integrated circuit is disclosed. In the present invention, a library containing predetermined wiring topologies is created. Each of the wiring topologies has an associated capacitive value. After extracting a layout topology of a segment of the metal wire, the layout topology is used to find and extract one of the predetermined wiring topologies in the library that corresponds to the layout topology. The associated capacitive value for the extracted wiring topology is used to calculate the total capacitance of the metal wire.

Capacitance estimation

Methods for calculating delays for cells in ASICs are disclosed. In the present invention, delays are computed by considering not only the process (P), voltage (V), temperature (T) but also input ramptime (R) and output load or fanout (F) of the cells by fitting the delay at four corner points for derated PVT condition into a non-linear equation which is a function of P, V, T, R and F. Thus, the delay is a five dimensional characterization, and the characterization is split into (P,V,T) characterization and (R,T) characterization to reduce the characterization time and resources. The present invention provides for accurate calculation of delays for cells in ASICs.

4K derating scheme for propagation delay and setup/hold time computation

A method of pin placement for an integrated circuit includes the steps of (a) receiving as input a corresponding set of pin constraints for each pin of a hard macro, (b) receiving as input a specification for the hard macro, (c) locating pin slots on each side of the hard macro, (d) finding at least one of a horizontal interval and a vertical interval on a side of the hard macro for each pin of the hard macro, and (e) assigning each pin of the hard macro to a pin slot within the horizontal interval and the vertical interval that satisfies the corresponding set of pin constraints.

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Sunnyvale, CA, United States of America

Charutosh Dixit