Altera Corporation

Charu Sardana

Raminda U Madurawe

Peter John McElheny

Richard G Smolen

Qi Xiang

Kyung Suk Oh

Peter Smeys

Yanzhong Xu

Albert Ratnakumar

Bradley Jensen

Guang Chen

An on-die-capacitor structure includes a first capacitor and a second capacitor. The first capacitor may have first and second terminals. The first and second terminals are directly connected to first and second power supply rail structures, respectively. The first power supply rail structure is different from the second power supply rail structure. The second capacitor may have third and fourth terminals. The second capacitor is connected in series between the second power supply rail structure and a third power supply rail structure. The third power supply rail structure is different from the first and second power supply rail structures. The third and fourth terminals are directly connected to the second and third power supply rail structures, respectively. The first capacitor may have a first capacitance and the second capacitor structure may have a second capacitance that is greater than the first capacitance.

On-die capacitor (ODC) structure

A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.

Programmable device with a metal oxide semiconductor field effect transistor

Integrated circuits with transistors and decoupling capacitor structures are provided. A decoupling capacitor structure may include multiple deep trench structures formed in a semiconductor substrate. The deep trench structures may each be lined with high-&#x3ba; dielectric material. A conductive metal layer for use in controlling threshold voltages associated with n-channel or p-channel devices may be formed over the high-&#x3ba; dielectric liner. Conductive material such as aluminum may be used to fill the remaining trench cavity. The high-&#x3ba; dielectric liner may be simultaneously deposited into the deep trench structures and gate regions of the transistors. In one suitable arrangement, the deep trench structures and transistor metal gates for at least a selected type of transistors may be formed in parallel. In another suitable arrangement, the deep trench structures and the transistor metal gates may be formed in separate steps.

Methods for fabricating deep trench capacitors

Provided is a high resistance value vertically-integrated semiconductor interconnect with resistance in the 10 k&OHgr;-10 G&OHgr; range, and a process to make such highly resistive interconnects together with low resistive interconnects in a precisely controllable manner. In addition, provided is an SRAM cell with highly resistive contact processing for a pull-up resistor.

Highly resistive interconnects

Provided is a high resistance value vertically-integrated semiconductor interconnect, and a process to make such highly resistive interconnects together with low resistive interconnects in a precisely controllable manner. In addition, provided is an SRAM cell with highly resistive contact processing for a pull-up resistor.

Growing community of inventors

San Jose, CA, United States of America

Charu Sardana