Cree Gmbh

Charlotte Jonas

Anant Kumar Agarwal

Qingchun Zhang

Sei-Hyung Ryu

John Williams Palmour

Lin Cheng

Sarit Dhar

Doyle Craig Capell

Craig Capell

David Grider

Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein.

Double guard ring edge termination for silicon carbide devices

A method of forming a transistor device include forming a drift layer of a first conductivity type, forming a well of a second conductivity type in the drift layer, forming a JFET region with first conductivity type dopant ions in the drift layer, forming a channel adjustment layer of the first conductivity type on the JFET region and the well, implanting first conductivity type dopant ions to form an emitter region of the first conductivity type extending through the channel adjustment layer and into the well, wherein the emitter region is spaced apart from the JFET region by the well, implanting second conductivity type dopant ions to form a connector region of the second conductivity type adjacent the emitter region, forming a gate oxide layer on the channel region, and forming a gate on the gate oxide layer.

High power insulated gate bipolar transistors

A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.

Vertical power transistor with built-in gate buffer

A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Field effect transistor devices with low source resistance

A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

Transistor with A-face conductive channel and trench protecting well region

A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region. The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.

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Morrisville, NC, United States of America

Charlotte Jonas