United Microelectronics Corp.

Other

Charlie Han

Min-Chih John Hsuan

Te-Sheng Yang

Kai-Kuang Ho

Pien Chien

Shih-Chin Lin

Jerry Jaw

Walx Fang

Min Chih Hsuan

Chin-Lung Hung

Wei-Hsiao Chen

Tazsheng Feng

Cheng-ju Hsieh

Tung-Chi Liu

Taisheng Feng

Ming-Huang Hung

This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and takes advantage of the length between the heat sink and the first mold packaged materials at the first axis to be about equal to the length between the chip and the second mold packaged materials at the first axis to prevent producing voids that would form unbalanceable thermal mold flow. The heat sink can also dissipate heat from the lead frame to others spaces in the integrated circuit packages. This method and means can prevent delaminating and cracking occurring in the chip and can increase the quality of integrated circuits.

Integrated circuit packages and the method for making the same

A method for determining failure rate and selecting a best burn-in time is disclosed. The method comprises the following steps. First of all, integrate circuits are provided. Then a life-time testing process is performed, wherein a failure rate versus testing time relation is established by measuring the life-time of each integrated circuit under a testing environment, wherein an acceleration factor function also is established under the testing environment. Next a simulating process that uses a testing time function is performed to simulate the failure rate versus testing time relation. Then a transforming process that uses the acceleration factor function is performed to transform the testing time function into a real time function. Finally, an integrating process is performed to integrate the real time function through a calculating region to acquire an accumulated failure rate real time function.

Method for determining failure rate and selecting best burn-in time

A backplane with multiple arrayed electrodes positioned on the backplane is provided in a method of fabricating a liquid crystal (LC) panel. The method begins with coating an alignment layer on the backplane. By performing a rubbing process, multiple alignment trenches are formed on the alignment layer. A photoresist layer is then formed on the alignment layer. By performing a lithography process, both a side frame, having at least one slit, and multiple photoresist spacers(PR spacers) are formed on the alignment layer. A gasket seal is coated on the side frame and the multiple PR spacers. By performing a lamination process, a transparent conductive layer is laminated on the backplane. A liquid crystal filling (LC filling) processis then performed to fill a cell gap between the backplane and the transparent conductive layer with liquid crystal. Finally, an end sealing process is performed to seal the slit.

Method of fabricating an LC panel

This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and take advantage of the length between the heat sink and the first mold packaged materials at the first axis to be about equal to the length between the chip and the second mold packaged materials at the first axis to prevent producing voids form unbalanceable thermal mold flow. The heat sink can also dissipating heat from the lead frame to others spaces in the integrated circuit packages. This method and means can prevent delaminating and cracking occurring in the chip and increasing the qualities in integrated circuits.

Integrated circuit packages and the method for the same

An architecture for wafer scale memories and a placement method replaces defective chips with spare chips in a memory module so as to provide minimum critical signal delay. The SDRAM memory chips are classified into normal chips and spare chips, where the normal chips are formed into groups such as rows or columns, and the spare chips are used to replace defective normal chips. A delay model for metal lines and vias is used to compute the signal delay for placement and routing. The placement problem is modeled as a bipartite graph and solved using a branch and bound algorithm to obtain a chip replacement configuration having the shortest critical signal delay. Also described is a hierarchical routing approach, which classifies the signals into different types and levels of signals. During fabrication, the replacement of defective chips with spare chips is accomplished by using two extra conductive layers and patterning the extra layers using a mask that is independent of the defect distribution of a particular wafer.

Placement and routing for wafer scale memory

A method of fabricating a direct contact through hole type wafer. Devices and contact plugs are formed in one side of a silicon-on-insulator substrate, and multilevel interconnects are formed over the side of the silicon-on-insulator substrate. The multilevel interconnects are coupled with the devices and the contact plugs. Bonding pads, which couples with the multilevel interconnects, are formed over the multilevel interconnects. An opening is formed on the other side of the silicon-on-insulator substrate to expose the contact plugs. An insulation layer, a barrier layer and a metal layer are formed in sequence in the opening. Bumps are formed on the bonding pads and the metal layer, respectively.

Method of forming package

A pad design. The pad design provides an additional testing pad that is electrically connected to a conventional bonding pad and positioned beside the bonding pad. The conventional bonding pad is formed on a provided chip, and a bump is formed on the bonding pad. A final test is performed on the testing pad so that damage formed on the bump or on the bonding pad can be prevented.

Pad design

A dual-dies packaging structure is provided. The dual-dies packaging structure includes a lead frame, which further includes a die pad and several lead legs, in which the die pad includes an upper surface and a lower surface. A first die, having several first bonding pads, is fixed on the upper surface of the die pad by, for example, gluing it. The first bonding pads remain exposed. A second die, having several second bonding pads, is fixed on the lower surface by, for example, gluing it. The second bonding pads remain exposed. A bumping redistribution structure layer is located on the second die so as to redistribute each of the second bonding pads to a pseudo-bonding pad. Each pseudo-bonding pad has its proper location with respect to the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other.

Dual-dies packaging structure and packaging method

An alternate-timing burn-in method suitable for testing a plurality of memory units on a wafer and capable of preventing any idling due to direct current timing. A first bit line voltage clocking signal is generated and sent to one terminal of any memory unit. A second bit line voltage clocking signal is generated and sent to the other terminal of the same memory unit. In addition, the edge of the second bit line voltage clocking signal corresponds to the mid-point of the first bit line voltage clocking signal.

Alternate timing wafer burn-in method

Method of fabricating direct contact through hole type

A direct contact through hole type wafer structure. Both sides of a wafer have devices and contacts. The contacts are coupled with the devices. Bumps are formed on the contacts, respectively.

Direct contact through hole type wafer structure

A preburn-in DRAM module circuit board is provided, which allows a plurality of DRAM modules to be constructed directly thereon, and which can be directly connected to a large burn-in oven so as to perform a burn-in process concurrently on the DRAM modules mounted thereon to check for any defected IC chips that are to be reworked. After the burn-in process, each of the DRAM modules can be cut apart from the circuit board to serve as a single memory module. The preburn-in DRAM module circuit board allows the manufacturing process for the DRAM modules to be reduced in schedule and manufacturing cost. Material cost can also be saved since the burn-in circuit and the module circuit are arranged on the same circuit board.

Preburn-in dynamic random access memory module and preburn-in circuit board thereof

A wafer level IC structure and a method of manufacturing this wafer level IC structure are proposed, which can help increase the yield of the IC manufacture. The wafer level IC structure is constructed on a semiconductor wafer which is defined into a plurality of discrete IC blocks on the wafer, each IC block being used to form a plurality of IC components such as memory cells. A multi-layer interconnect structure is formed to electrically interconnect these IC components in each of the IC blocks. A first testing and repair process is then perform to disconnect any inoperative IC components from active use. This completes the fabrication stage of the manufacture process. In the subsequent packaging stage, a redistribution line structure is formed to interconnect the discrete IC blocks into an integral functional unit. A second testing and repair process is then perform to disconnect any inoperative IC blocks from active use. The overall IC manufacture would have an increased yield as compared to the prior art.

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Hsinchu Hsien, Taiwan

Charlie Han