Agere Systems Inc.

Agere Systems Guardian Corp.

Western Electric Company, Inc.

Other

Texas Instruments Corporation

Bell Telephone Laboratories

Lucent Technologies Inc.

At&t Bell Laboratories

Charles Walter Pearce

Sailesh Chittipeddi

Pradip Kumar Roy

Christopher Boguslaw Kocon

Simon John Molloy

Muhammed Ayman Shibib

John Manning Savidge Neilson

Haian Lin

Wen Lin

Bryan Chaeyoo Chung

Sailesh Mansinh Merchant

William Graham Easter

Frank Miceli

John A Maze, Iii

Robert J Lavigna

Kevin Paul Yanders

Raymond E Reusser

Vincent Joseph Zaleckas

Gary Eugene Daum

James T Clemens

Bryan C Chung

Robert John Griffin

Paul F Schmidt

James T Nelson

Robert C Sun

Dinesh A Mehta

Robert William Criscuolo

Michael Steven Billig

Gerald N DiBello

Glenn Alan Marshall

Kevin P Yanders

Patricia Pearce

Jeffrey Kenneth Haas

Daniel Joseph McKee

A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.

High voltage channel diode

A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.

High voltage power integrated circuit

A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.

Method of manufacturing a laterally diffused metal oxide semiconductor device

A laterally diffused metal oxide semiconductor (LDMOS) device and a method of manufacture therefor. The method of manufacturing the LDMOS device includes forming an amorphous region in a semiconductor substrate between isolation structures and adjacent a gate structure, by implanting an amorphizing element, such as silicon or germanium, in the semiconductor substrate. The method further includes diffusing a channel dopant laterally in the amorphous region, to form a first portion of a channel.

Method for manufacturing a laterally diffused metal oxide semiconductor device

The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.

Semiconductor device having a doped lattice matching layer and a method of manufacture therefor

The invention includes a laterally diffused metal oxide semiconductor transistor comprising a gate electrode and comprising tapered oxide self aligned to the gate electrode.

LDMOS device having a tapered oxide

A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.

Trench capacitors in SOI substrates

The present invention relates to an apparatus and method for polishing substrate surfaces. The method can include the steps of holding a substrate against a polishing surface and depositing slurry on the polishing surface. The method can further include the step of moving the holding device in a substantially curvilinear path relative to the polishing surface, or the step of moving the polishing surface in a substantially curvilinear path relative to the holding device. The apparatus comprises a polishing surface, a holding device for holding a substrate against the polishing surface, and a slurry supply system for depositing slurry on the polishing surface. The apparatus further includes a moving structure for moving the holding device in a substantially curvilinear path along the polishing surface, or a moving structure for moving the polishing surface in a substantially curvilinear path relative to the holding device. The substantially curvilinear path is preferably substantially a figure eight path.

Curvilinear chemical mechanical planarization device and method

The invention includes a laterally diffused metal oxide semiconductor transistor comprising a gate electrode and comprising tapered oxide self aligned to the gate electrode and a method of making the transistor.

Use of selective oxidation to improve LDMOS power transistors

The invention includes a method of etching silicon dioxide, comprising doping a layer of silicon dioxide to form a layer of doped silicon dioxide and etching the doped silicon dioxide layer with phosphoric acid.

Oxide etch

An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiN ) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta O ) layer. The SiN cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer Si N /Ta O /Si N structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the Si N /Ta O /Si N structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the Si N /Ta O /Si N structure.

Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers

The present invention provides a method of manufacturing a semiconductor device, and a related method manufacturing an integrated circuit. In one embodiment, the method of manufacturing a semiconductor device includes creating a source/drain region between an electrode and an isolation structure located on a substrate. The method further includes implanting a dopant at a predetermined implant dopant concentration through an opening formed in a channel stop mask and located between the electrode and the isolation structure to form a channel stop between the source/drain region and the isolation structure.

Method of manufacturing a channel stop implant in a semiconductor device

Method for forming trench capacitors in SOI substrates

Growing community of inventors

Emmaus, PA, United States of America

Charles Walter Pearce