Xilinx, Inc.

Microsoft Technology Licensing, LLC

Rambus Inc.

Mosys, Inc.

Magnalynx, Inc.

Cadence Design Systems, Inc.

Synopsys, Inc.

Charles Walter Boecker

Eric Douglas Groen

William C Black

Masum Hossain

Scott Alan Irwin

Nhat M Nguyen

Aaron Hoelscher

Joseph Neil Kryzak

Andrew G Jenkins

Barry Thompson

Winston Allen Saunders

Paolo Costa

Kai Shi

Niranjan Achugundla Puttaswamy

Aldo Bottelli

Matthew Shafer

Haidang Lin

David Black

Christian L Belady

Brian Taylor Brunn

Jeffrey Neil Margolis

Roxanne T Vu

Chuan Pu

Shaishav A Desai

Douglas M Carmean

Hitesh Ballani

Prashant Choudhary

Lisa Ru-feng Hsu

Bupesh Pandita

Sheethal Somesh Nayak

Eric Groen

Derek L Knee

Michael Raymond Trombley

Jouya Jadidian

Michael J Gaboury

Anirban Banerjee

Richard P Rouse

Ping Lu

Ariel Gomez Diaz

Daniel Jonathan Finchley Cletheroe

Lawrence Albert Prather

Alvin Wang

Foteini Karinou

Yiqin Chen

Piyush Abhay Hatolkar

Junyi Liu

Maya Subhadra

Chethan Rao

Marijn Petrus Gerardus Rombouts

Simon S Li

Md Masum Hossain

Asad Azam

Ravi Shivnaraine

Sokratis Vamvakos

Edwin Magtoto Gozun

Terrence Huat Hin Tan

Vasily Lyutsarev

Shawn Yohanes Siew

Kaoutar Benyahya

Scott A Irwin

Joseph N Kryzak

Aaron J Hoelscher

A transmission method comprising: encoding a message into error correction coding blocks, each comprising a different portion of the payload bits of the message and a respective plurality of error correction bits; and applying an interleaving map to error correction coding blocks, such that for each error correction coding block, different bits of the error correction coding block are mapped to different channels, each channel thus being used to transmit bits from a respective selection of multiple of the error correction coding blocks. Thus, for at least one channel failure scenario in which at least one of the plurality of channel fails leaving a plurality of remaining channels, enough bits will remain on the remaining channels to enable correction of the message based on the error correction coding.

Error-resistant data communication using multiple channels

Systems and methods for isolating faults in die-to-die interconnects are provided. A method includes providing a first transmission path, along a die-to-die interconnect, from a transmitter associated with a first die to an asynchronous buffer associated with a second die. The method further includes providing a second transmission path from voltage reference circuitry associated with the second die to the asynchronous buffer associated with the second die. The method further includes simultaneously enabling both the first transmission path and the second transmission path to allow the asynchronous buffer to receive inputs from both the transmitter associated with the first die and the voltage reference circuitry associated with the second die, such that the inputs received by the asynchronous buffer are indicative of: (1) no failure in the die-to-die interconnect, (2) an open failure in the die-to-die interconnect, or (3) a short failure in the die-to-die interconnect.

Systems and methods for isolating faults in die-to-die interconnects

Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.

Synchronization of integrated circuit dies that contain a processor and clock generator by adjusting delay lines based on phase count

Examples are provided that relate to determining a capacitance based on a charge accumulated on a sense capacitor electrode. One example provides a head-mounted device comprising a facial-tracking sensor, a controller, and a charge sensing circuit connected to the facial-tracking sensor. The facial-tracking sensor includes a sense capacitor electrode configured to be positioned proximate to a surface of a face and form a capacitance based upon a distance between the sense capacitor electrode and the surface of the face, and the controller configured to apply a reference voltage to the sense capacitor electrode. The charge sensing circuit is configured to determine the capacitance of the sense capacitor electrode by determining an amount of charge accumulated on the sense capacitor electrode resulting from the reference voltage.

Determining charge on a facial-tracking sensor

A display device includes a display substrate and a backplane substrate. The display substrate includes an array of micro-LEDs forming individual pixels. The backplane substrate includes a plurality of pixel logic hardware modules. Each pixel logic hardware module includes a local memory element configured to store a multi-bit pixel intensity value of a corresponding micro-LED for an image frame. The backplane substrate is bonded to a backside of the display substrate such that the pixel logic hardware modules are physically aligned behind the array of micro-LEDs and each pixel logic hardware module is electrically connected to a micro-LED of the corresponding pixel.

Micro-LED display

A domain control circuit includes a power regulator to supply power for a first domain on a power rail and a sequencing circuit to control the power regulator, and a clock gate signal to activate the domain. The sequencing circuit receives a domain control signal to control activation and deactivation of the domain. The domain control circuit deactivates the clock gate signal to the domain after controlling the power regulator to supply power for the domain on a power rail. In this manner, a voltage droop in a supply voltage on a power rail is reduced. In some examples, the clock gate signal to the domain is deactivated after a voltage increase on the power rail. In some examples, the power regulator includes a plurality of parallel regulator circuits and a regulator control circuit to determine a number of the parallel regulator circuits to be activated to power the domain.

Domain clock and power activation control circuit to reduce voltage droop and related methods

A current-mode transmitter amplifies a differential input signal to a differential, current-mode output signal. A split-input, current-mode-logic stage produces small, analog signals to limit switching currents and thus power consumption and power-supply noise. These small, analog signals are driven through a source-follower stage to reduce loading and shift the common-mode voltage to a desired level. A switched-current-source H-bridge driver combines differential outputs from the source-follower stage to provide an amplified differential output current. The output swing from the H-bridge driver is controlled by the voltage level from the source follower and derived from a replica-bias structure.

Direct-switching h-bridge current-mode drivers

A digital signal processor includes analog to digital converters to convert an analog voltage to digital voltage in unit intervals of an analog signal. A decision feedback equalizer (DFE) determines a first level of a digital sum of a digital voltage in a first UI and digital voltages of adjacent UIs (taps). The DFE identifies predetermined sequences of levels of consecutive UIs that include the first level and selects one of the predetermined sequences to decode digital data encoded in the analog signal in the UI. The DSP may be programmable to include taps from UIs that may affect the first UI. The predetermined sequences may include levels of the digital sums of consecutive UIs of the analog signal. The predetermined sequences may be identified in a look-up table based on the first level.

Digital signal processors providing scalable decision feedback equalization (DFE) employing sequence selection and related methods

A system for interconnecting a plurality of computing nodes includes a plurality of optical circuit switches and a plurality of electrical circuit switches. A first network stage comprises a first plurality of circuit switches selected from among the plurality of optical circuit switches and the plurality of electrical circuit switches. Each computing node among the plurality of computing nodes is optically coupled to at least one of the first plurality of circuit switches. A second network stage comprises a second plurality of circuit switches selected from among the plurality of optical circuit switches and the plurality of electrical circuit switches. Each circuit switch among the first plurality of circuit switches is optically coupled to each circuit switch among the second plurality of optical circuit switches.

Efficiently interconnecting a plurality of computing nodes to form a circuit-switched network

A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitryresolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.

Methods and circuits for decision-feedback equalization with early high-order-symbol detection

A phase-locked loop (PLL) circuit generates an analog signal in phase-lock with a reference signal at a reference frequency. The PLL circuit includes a charge pump circuit, a loop filter circuit, a feedback divider, and a voltage controlled oscillator (VCO). The charge pump circuit charges a sample capacitor of the loop filter circuit to a sample voltage based on a phase difference between the generated analog signal and the reference signal. The loop filter circuit stores the sample voltage as a proportional control voltage in a hold capacitor to reduce or avoid ripple in the control voltage that causes jitter in the analog signal. The loop filter circuit also provides the sample voltage to an integral component circuit comprising a comparator and digital accumulator producing an integral control. The VCO generates the analog signal at a frequency based on the proportional control voltage and the integral control voltage.

Phase-locked-loop circuit employing a hybrid loop filter with sample and hold capacitors for reduced signal jitter, and related methods

Analog calibration (ACAL) circuits supporting iterative measurement of an input signal from a measured circuit, and related methods are disclosed. The ACAL circuit includes a voltage reference generation circuit and a comparator circuit. The voltage reference generation circuit is configured to provide an input reference voltage. The comparator circuit is configured to compare the input reference voltage to an input circuit voltage of a measured circuit and generate a digital measurement signal based on the comparison. To provide for the ACAL circuit to more precisely measure the input circuit voltage, the voltage reference generation circuit is programmable and is configured to a generate the input reference voltage based on a programmed reference voltage selection. In this manner, the ACAL circuit can be used to measure the input circuit voltage in an iterative manner based on different programmed input reference voltages for a more precise measurement of the input circuit voltage.

Programmable analog calibration circuit supporting iterative measurement of an input signal from a measured circuit, such as for calibration, and related methods

A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.

Serial-link receiver using time-interleaved discrete time gain

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitryresolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

Symbol-rate phase detector for multi-PAM receiver

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Ames, IA, United States of America

Charles Walter Boecker