International Business Machines Corporation

Globalfoundries Inc.

Kabushiki Kaisha Toshiba

Freescale Semiconductors Inc.

Globalfoundries U.S. 2 LLC

Charles W Koburger, Iii

David V Horak

Toshiharu Furukawa

Steven J Holmes

Mark Charles Hakey

Shom Ponoth

Chih-Chao Yang

Peter H Mitchell

Larry Alan Nesbit

Jack Allan Mandelman

Veeraraghavan S Basker

William R Tonti

Marc Adam Bergendahl

Kangguo Cheng

Ali Khakifirooz

Mark Eliot Masters

Chung H Lam

Elbert Emin Huang

Ethan Harrison Cannon

Jerome Brett Lasky

Bruce Bennett Doris

Robert J Gauthier, Jr

Balasubramanian S Haran

James Albert Slinkman

Gerhard Ingmar Meijer

Douglas C La Tulipe, Jr

John Gerard Gaudiello

Toshijaru Furukawa

Hemanth Jagannathan

Kirk David Peterson

Su Chen Fan

Naim Moumen

John H Givens

Ruilong Xie

Theodorus E Standaert

Jed Hickory Rankin

Sivananda K Kanakasabapathy

Christopher J Penny

Xiuyu Cai

Wai-Kin Li

Yunpeng Yin

Randy William Mann

James Spiros Nakos

Shyng-Tsong Chen

Paul Christian Parries

Stanislav Polonsky

Leathen Shi

Samuel S Choi

Karen Elizabeth Petrillo

Jonathan Daniel Chapple-Sokol

Francis Roger White

Christopher Frederick Robinson

Shunhua Thomas Chang

Mariko Takayanagi

Michael James Lercel

Kurt R Kimmel

Michael L Kerbaugh

Susan S Fan

Leah Marie Pfeifer Pastel

Krishna V Singh

Peter Zeitzoff

John Edward Cronin

Robert Russell Robison

Dominic Joseph Schepis

John Joseph Pekarik

Bomy A Chen

Qiqing Christine Ouyang

William F Clark, Jr

Stephen Ellinwood Luce

Christopher Joseph Waskiewicz

Gregory Breyta

Michael John Hargrove

Michael D Armacost

Kenneth John Giewont

Carter W Kaanta

Daniel A Corliss

James Allan Bruce

Junedong Lee

Eric Adler

Dale J Pearson

John W Golz

Ronald R Troutman

Brian J Machesney

Jin J Wu

Xuefeng Hua

Henry J Geipel, Jr

Teresa Jacqueline Wu

John R Abernathey

Neena Garg

Wayne I Kinney

Ning Hsieh

Isabel Ying Yang

Qiqing C Quyang

Carol Boye

Somanath Dash

John Joseph Prxarik

James Allen Bruce

Susan F Cronin

Shom Pomoth

Nitin B Parekh

A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.

Size-filtered multimetal structures

A structure including a plurality of fins etched from a semiconductor substrate, a gate electrode above and perpendicular to the plurality of fins, a pair of sidewall spacers disposed on opposing sides of the gate electrode, a gap fill material above the semiconductor substrate and between the plurality of fins, the gap fill material is directly below the gate electrode and directly below the pair of sidewall spacers, wherein the gate electrode separates the gap fill material from each of the plurality of fins, and an epitaxially grown region above a portion of the plurality of fins not covered by the gate electrode, the EPI region separates the gap fill material from each of the plurality of fins.

FinFET with reduced capacitance

A method including depositing a gap fill material on top of a conformal dummy gate oxide above and in between a plurality of fins, forming one or more openings between the plurality of fins and the gap fill material by selectively removing a portion of the conformal dummy gate oxide, and forming a gate within the one or more openings, and above the plurality of fins and the gap fill material.

A structure including a gate electrode above and perpendicular to a plurality of semiconductor fins, a pair of spacers disposed on opposing sides of the gate electrode, and a gap fill material above a semiconductor substrate, directly below the gate electrode, and between the plurality of fins, the gate electrode separates the gap fill material from each of the plurality of fins.

Finfet with reduced capacitance

A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.

Replacement gate electrode with a self-aligned dielectric spacer

Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Self-aligned dielectric isolation for FinFET devices

A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

Borderless contact structure

A fin field effect transistor (FinFET) device and a method of fabricating the FinFET are described. The device includes a fin formed on a substrate, the fin including a channel region of the device and a spacer and a cap formed over a dummy gate line separating a source and drain of the device. The device also includes an epitaxial layer formed over portions of the fin, the epitaxial layer being included between the fin and the spacer.

Under-spacer doping in fin-based semiconductor devices

An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).

Integrated circuit structure having selectively formed metal cap

A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.

Silicon-on-insulator transistor with self-aligned borderless source/drain contacts

An finFET structure including a plurality of fins etched from a semiconductor substrate, a plurality of gates above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gates, and a gap fill material above the semiconductor substrate, below the gate, and between the plurality of fins, wherein the gate separates the gap fill material from each of the plurality of fins.

A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

Dual damascene dual alignment interconnect scheme

Growing community of inventors

Delmar, NY, United States of America

Charles W Koburger, Iii