At&t Bell Laboratories

Bell Telephone Laboratories

Charles W Hoffner, Ii

Wing N Toy

Walter T Hartwell

David L Hinshaw

Disclosed is a method and apparatus for interfacing N bit-serial communication channels to an N-bit parallel communication channel. The serial channels are interfaced simultaneously, i.e., during a single bit time, with the parallel channel by an interface unit that is shared by the serial channels. The interface unit is microprocessor based. To service all serial channels simultaneously, the microprocessor's interface program divides each bit interval into 2N time slots and allocates two time slots per bit interval to each of the N channels, one time slot for functions associted with receipt of bits from the serial channel and transmittal thereof on the parallel channel, and one time slot for functions associated with receipt of data from the parallel channel and transmittal thereof on the serial channel. At the beginning of each time slot the program causes an updated word to be transmitted to the serial channels, one bit to each channel, and a sample word to be received from the serial channels, one bit sample from each channel. The program identifies the samples of centers of the bits received from the serial channels and uses these as the received bit values.

Multichannel interface

A word organized random access memory comprises a plurality of circuit packs arranged such that the memory capacity can be easily increased or decreased in increments corresponding to the word capacity of a single circuit pack while distributing the power dissipation associated with accessing a word across a plurality of the circuit packs. Each circuit pack comprises two or more independently accessible memory modules with each module arranged to store a plurality of word segments each of which comprises corresponding segments of different memory words. Input, output, and control wiring is provided such that access control of the circuit packs associates the packs into a chain which is looped back on itself. Links of this chain comprise groups of modules which define memory word locations wherein no two modules of a group are packaged on the same circuit pack. Loop around connections complete groups by interconnecting incomplete groups from the end of the chain with complementary incomplete groups from the beginning of the chain. The capacity of the memory is increased or decreased by adding or deleting one or more circuit packs in the chain. Switches are provided to accommodate the insertion or deletion of a circuit pack.

Growing community of inventors

Naperville, IL, United States of America

Charles W Hoffner, Ii