International Business Machines Corporation

Intellectual Business Machines Corporation

Charles W Gainey, Jr

Damian Leo Osisek

Mark S Farrell

Jeffrey Paul Kubala

Dan F Greiner

Timothy John Slegel

Donald W Schmidt

Lisa Cranton Heller

Gustav E Sittmann, Iii

Jonathan D Bradbury

Marcel Mitran

Michael K Gschwind

Harry M Yudenfriend

Fadi Y Busaba

Kenneth J Oakes

Chung-Lung K Shum

Frank William Brice

Steven G Glassen

Robert R Rogers

Eric M Schwarz

Peter Kenneth Szwed

Charles E Shapley

Peter Grimm Sutton

Elpida Tzortzatos

Peter Dana Driever

Leslie W Wyman

Ugochukwu Charles Njoku

Tan Lu

James H Mulder

Thomas B Mathias

Steven R Carlough

Erwin F Pfeffer

Reid T Copeland

Bernard R Pierce

Brian L Smith

Christian Jacobi

Thomas Anthony Gregg

David F Craddock

Charles Franklin Webb

Beth A Glendening

Marten J Halma

Klaus Werner

Klaus Meissner

Daniel Francis Casper

Kevin Alexander Stoodley

Janet R Easton

Hans-Helge Lehmann

Scott M Carlson

Richard K Errickson

Carol B Hernandez

John S Trotter

John R Flanagan

Allan Samuel Meritt

Greg A Dyck

Anthony F Coneski

Mark A Wisniewski

Matthew J Kalos

Roger Gregory Hathorn

Dale Francis Riedy, Jr

Colin Beaton Verrilli

Richard Louis Arndt

Catherine C Huang

Steven A Bade

Eugene P Hefferon

Thomas J Dewkett

Helmut H Weber

Nia Letise Kelley

Siegfried Sutter

Robert A Smith

Louis C Ricci

Ugochukwu Njoku-Charles

Paul Gregory Greenstein

Richard Loise Arndt

Mark Anthony Check

Frank Siegfried Lehnert

Bernd Nerz

John Robert Ehrman

John Ted Rodell

Peter Jeremy Relson

Timothy J Siegel

Mike Stephen Fulton

Stephen G Wilkins

Kenneth M Trowell

Charles E Webb

Duane C Hughes

Kathleen M Walsh

Samuel L Wentz

James C Daly

Harvey Tildon McGee

William K Kelley

Roberto J Sanchez

David W Hollar

Arthur K Fitzgerald

Cynthia Sittmann, Legal Representative

Arthur M Day

Mary B Crisman

Werner Wicke

Matthias Gubitz

Ugochukwo Njoku-Charles

Michael G Melendy

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Configure storage class memory command

A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

Efficiency for coordinated start interpretive execution exit for a multithreaded processor

A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of architectural modes and has a defined power-on sequence that is to power-on the computing environment in one architectural mode of the plurality of architectural modes. Based on determining that the configuration architectural mode facility is installed, the computing environment is reconfigured to restrict use of the one architectural mode. The reconfiguring includes selecting a different power-on sequence to power-on the computing environment in another architectural mode of the plurality of architectural modes, wherein the another architectural mode is different from the one architectural mode, and executing the different power-on sequence to power-on the computing environment in the another architectural mode in place of the one architectural mode restricting use of the one architectural mode.

Architectural mode configuration

A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of architectural modes and has a defined power-on sequence that is to power-on the computing environment in one architectural mode of the plurality of architectural modes. Based on determining that the configuration architectural mode facility is installed, the computing environment is reconfigured to restrict use of the one architectural mode. The reconfiguring includes selecting a different power-on sequence to power-on the computing environment in other architectural mode of the plurality of architectural modes, wherein the other architectural mode is different from the one architectural mode, and executing the different power-on sequence to power-on the computing environment in the other architectural mode in place of the one architectural mode restricting use of the one architectural mode.

What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.

Dynamic address translation with access control in an emulator environment

A system and method of implementing a wait state for a plurality of threads executing on a computer processor core of the processor. The processor is configured to execute instruction streams by the plurality of threads, wherein the plurality of threads includes a first thread and a set of remaining threads and determine that the first thread has entered a first wait state loop. The processor is also configured to determine that any of the set of remaining threads has not entered a corresponding wait state loop and remain by the first thread in the first wait state loop until each of the set of remaining threads has entered the corresponding wait state loop.

A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.

Compare and delay instructions

Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Performing an operation absent host intervention

A facility is provided that, when installed, removes from an architecture a selected architectural function, such that the function is not able to be turned on/off regardless of other controls within the environment. When the facility is installed, the architectural function is not supported when processing in an architectural mode based on the architecture. It is as if the selected architectural function is no longer available in the architecture, and in fact, the code implementing the facility may have been deleted, bypassed, or otherwise eliminated. One such architectural function is virtual address translation, such as dynamic address translation (DAT), and the architecture is, for instance, ESA/390.

Managing processing associated with selected architectural facilities

Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

Convert to zoned format from decimal floating point format

Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

Interruption facility for adjunct processor queues

In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.

Execution of an instruction for performing a configuration virtual topology change

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Poughkeepsie, NY, United States of America

Charles W Gainey, Jr