International Business Machines Corporation

Charles W Evans

Benedicto U Messina

James R Robinson

Ethel L Richardson

Frederick O Flusche

Joseph A Wetzel

Inhibit means prevents a store-in-cache (SIC) from requesting or receiving any line fetch from MS when a clear line (CL) command is issued by a CPU to main storage (MS). Two CPU modes are provided: (1) an initial storage validation mode and (2) an instruction processing mode. The system operator controls the first mode so that a CPU can execute the CL command during system initialization without any prior data fetch from MS. In the second mode, the CL command is executed as a component of a program instruction fetched from MS that can clear a block in main storage. In a multiprocessor (MP), the CL command by any CPU requests a line store of pad data into an addressed line in MS only after each other SIC copy directory is searched and any found conflicting line is invalidated. Line castout to MS is prohibited for a conflicting line found in a cache by the CS command, which would have been a normal operation for other types of CPU commands. After any line conflict is found for any other cache in the MP, the completion of the CL command is delayed by cancelling the line pad write request to MS. Then the IE repeatedly reissues the CL command until all found conflicting lines are invalidated. As soon as no conflict is found in any copy directory, the currently issued CL command is completed by not cancelling the pad data request to MS, so that pad bytes are then written into the line in MS.

Store-in-cache processor means for clearing main storage

A branch-address translation register (BAXR) is loaded by a current or a prior control word field. A word selection decoder circuit receives the BAXR outputs and combines them with machine-status signals to generate a word selection signal for selecting a control word from a currently accessed branch group in the control store. A BAXR switching circuit is also provided so that any control word can switch off the BAXR output and cause a control word selection without translation. The invention can obtain any required degree of addressing flexibility in microcode branch selection, i.e. from partial to total flexibility.

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Poughkeepsie, NY, United States of America

Charles W Evans