General Electric Company

Epic Technologies, Inc.

Integrated System Assemblies Corporation

Other

Lockheed Martin Corporation

Martin Marietta Corporation

Insulating Materials Incorporated

Charles W Eichelberger

Robert J Wojnarowski

James E Kohl

Walter J Butler

Edward B Miller

James F Bedard

Scott E Cutler

Kenneth B Welles, Ii

Salvatore F Nati, Jr

Kenneth Brakeley Welles

William P Kornrumpf

Abraham Auerbach

Michael A Haase

Herbert S Cole

James Wilson Rose

Wesley K Waldron

Rudolph A Dehn

Peter I Cohen

Lionel M Levinson

Lowell Scott Smith

Homer H Glascock, Ii

Constantine A Neugebauer

Charles E Thomas

Michael Gdula

Joseph Edward Piel, Jr

William D Ryckman

Richard O Carlson

Thomas M O'Loughlin

Paul V Starenas

Thomas P Wacker

Walter M Marcinkiewicz

Charles L Devlin

Philip Melvin Garratt

Michael E Rickley

De-Yu Chen

Salvator F Nati, Jr

Theodore G Mihran

Robert J Wojnarowksi

Wiliam P Kornrumpf

Edward S Andrejko

Methods of fabricating a circuit structure are provided. The fabrication method includes: forming a chip layer, which includes obtaining at least one chip and disposing a structural material around and physically contacting the side surface(s) of each chip in the chip layer. The structural material has an upper surface substantially coplanar with or parallel to an upper surface of each chip and defines at least a portion of a front surface of the chip layer, and has a lower surface substantially coplanar with or parallel to a lower surface of each chip, which defines at least portion of a back surface of the chip layer. The method further includes forming at least one strengthening structure over the back surface of the chip layer. The strengthening structure is formed to strengthen an interface between the chip(s) and the structural material.

Method of fabricating a circuit structure

Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.

Integrated thermal structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system

A method of bonding two structures together with an adhesive line of controlled thickness is provided. The method includes: applying an adhesive of controlled thickness to a first surface of a first structure; at least partially curing the adhesive; applying additional adhesive to the partially cured adhesive applied to the first surface or to a second surface of a second structure; holding the first structure and the second structure in alignment with the first surface and the second surface disposed in spaced, opposing relation; applying a force to the first structure and/or the second structure to squeeze the additional adhesive between the second surface and the partially cured adhesive applied to the first surface to reduce a thickness of the additional adhesive; and at least partially curing the additional adhesive to bond the first and second structures together.

Method of bonding two structures together with an adhesive line of controlled thickness

Methods of fabricating a base layer circuit structure are provided. One fabrication method includes: providing an alignment carrier having a support surface; forming a plurality of electrically conductive structures above the support surface of the alignment carrier; disposing a structural material around and physically contacting the side surfaces of the electrically conductive structures formed above the support surface, the structural material having an upper surface coplanar with or parallel to the upper surface of one or more of the electrically conductive structures; exposing, if covered, the upper surfaces of the electrically conductive structures to facilitate electrical connection to the structures; and separating the alignment carrier from the base layer circuit structure. The base layer circuit structure includes the plurality of electrically conductive structures and the structural material surrounding and physically contacting the electrically conductive structures.

Method of fabricating a base layer circuit structure

Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system

Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its upper surface and openings exposing its contact pads; electrically conductive structures; and structural dielectric material surrounding the side surfaces of the chips and the conductive structures. Each chips-first layer further includes a metallization layer on the front surface of the layer, residing at least partially on the pad mask and extending over an edge of the chip. Together, the pad mask and the structural material electrically isolate the metallization layer from the chip. Input/output interconnect structures physically and electrically contact the metallization layer over the front surface and/or the lower surfaces of the electrically conductive structures at the back surface of the chips-first layer, to facilitate input/output connection to chips of the layers in a stack.

Stackable circuit structures and methods of fabrication thereof

Electronic modules and methods of fabrication are provided implementing a first metallization level directly on a chips-first chip layer. The chips-first layer includes chips, each with a pad mask over an upper surface and openings to expose chip contact pads. Structural dielectric material surrounds and physically contacts the side surfaces of the chips, and has an upper surface which is parallel to an upper surface of the chips. A metallization layer is disposed over the front surface of the chips-first layer, residing at least partially on the pad masks of the chips, and extending over one or more edges of the chips. Together, the pad masks of the chips, and the structural dielectric material electrically isolate the metallization layer from the edges of the chips, and from one or more electrical structures of the chips in the chips-first layer.

Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer

Packaged electronic modules and fabrication methods thereof implementing a cell phone or other electronic system

Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system

Structure and method for temporarily holding at least one integrated circuit chip during packaging thereof are presented. A support plate has a release film secured to a main surface thereof. The support plate and release film allow UV light to pass therethrough. A UV curable chip adhesive is disposed over the release film for holding the at least one integrated circuit chip. After placement of the at least one integrated circuit chip in the UV curable chip adhesive, the UV curable chip adhesive is cured by UV light shone through the support plate and release film. As one example, the release film includes a UV release adhesive and the UV curable chip adhesive and UV release adhesive have a differential response to UV light which allows curing of the UV curable chip attach without release of the UV release adhesive.

Structure and method for temporarily holding integrated circuit chips in accurate alignment

Structures and methods are provided for electrically interconnecting and absorbing stress between a first electrical structure and a second electrical structure. In one embodiment, non-conductive compliant bumps are disposed on at least one of the structures and a metal layer is provided over a surface of the non-conductive compliant bumps. The metal layer facilitates electrical coupling of the metal on the surfaces of the compliant bumps with multiple contact pads of the structure supporting the bumps. The non-conductive compliant bumps can be fabricated of a low modulus material which has a high ultimate elongation property (LMHE dielectric). The LMHE dielectric can have a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least twenty percent. In an alternate embodiment, at least one mushroom-shaped conductive bump is disposed above a compliant dielectric layer on one of the first electrical structure or the second electrical structure. The mushroom-shaped conductive bumps are employed to electrically interconnect the first and second electrical structures. The compliant dielectric layer can be a LMHE dielectric.

Compliant, solderable input/output bump structures

Structures and methods are provided for absorbing stress between a first electrical structure and a second electrical structure connected together, wherein the first and second structures have different coefficients of thermal expansion. A dielectric material is disposed on at least one of the first and second electrical structures. This dielectric material is a low modulus material which has a high ultimate elongation property (LMHE dielectric). Preferably, the LMHE dielectric has a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least 20 percent. The LMHE dielectric can be photo patternable to facilitate formation of via openings therein and a metal layer is formed above the LMHE dielectric which has conductors capable of expanding or contracting with the dielectric. Conductors of the metal layer disposed above the dielectric and connected to vias in the dielectric have a length significantly greater than the maximum displacement due to thermal expansion between the first and second electrical structures, e.g., a length which is at least five times the displacement.

Integrated circuit structures and methods employing a low modulus high elongation photodielectric

Growing community of inventors

Schenectady, NY, United States of America

Charles W Eichelberger