Westinghouse Electric Corporation

Charles W Brooks

Donald R Lampe

William L Price

A digital signal processing system and more especially a programmable bulk memory included therein comprising a plurality of memory sections independently controlled and simultaneously operative for transferring blocks or vectors of digital data words directly between selected memory sections and external data handling units while maintaining the corresponding variety of data handling throughput rates thereof without the need for input-output buffer type memories coupled therebetween is disclosed. A method of addressing the sections of addressable memory locations for accessing therefrom and storing therein blocks of data words in accordance with predetermined sequences is also disclosed.

Programmable interface memory

A method and apparatus for multiplying a plurality of samples of first and second analog signals and summing the products there obtained. In stages of a first charge coupled device (CCD), charge packets corresponding to samples of the first analog signal are separated by charge packets corresponding to a first bias potential. In stages of a second CCD, charge packets corresponding to samples of the second analog signal are separated by charge packets corresponding to a second bias potential. In each step, a sum-of-products of samples and bias potentials is obtained. In circuitry coupled to the CCDs including switches and charge storage devices, the switches are operated to charge the charge storage devices with current or charges corresponding to sums-of-products of the signal samples and the bias potentials so as to provide via an output charge storage device, current corresponding to only the sums-of-products of the samples of the first and second analog signals without erroneous contributions due to multiplier threshold non-uniformities. Apparatus implementing the method can perform such functions as auto-correlation, cross-correlation, convolution, transversal filtering, and analog matrix multiplication, for example. In one aspect of the apparatus of the present invention, a first charge transfer analog delay means includes one charge transfer shift register channel and a second charge transfer delay means includes two charge transfer shift register channels. Each of said shift register channels includes a plurality of stages for holding and propagating charge packets. In a different aspect of the apparatus of the present invention, two charge transfer delay means each include two charge transfer shift register channels. In each of the aforementioned aspects of the invention, the device correlates, for example, analog signals propagating through the first analog delay means against analog signals propagating through the second analog delay means.

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Annapolis, MD, United States of America

Charles W Brooks