International Business Machines Corporation

Charles T Kroll

Geoffrey B Stephens

Arup Bhattacharyya

Paul A Farrar

Robert Michael Geffken

Madhukar L Joshi

Ronald R Silverman

William Andrew Keenan

Anthony J Hoeg, Jr

A dual electron injection structure (DEIS) and process for incorporating it into a semi-conductor structure, such as an E2PROM and/or NVRAM, is disclosed. The DEIS includes a composite structure formed from a layer of silicon rich nitride, a layer of silicon dioxide (SiO.sub.2) and a layer of silicon rich oxide. Preferably, a Plasma Enhanced Chemical Vapor Deposit (PECVD) method or a low pressure chemical vapor deposit (LPCVD) method is used to place the DEIS between the Poly 1 and Poly 2 devices of the semi-conductor structure.

Dual electron injection structure and process with self-limiting

A process for placing non-continuous Dual Electron Injection Structures (DEIS) between two layers of polysilicon used to form an array of poly devices on an integrated circuit substrate. Separate masks are used to define Poly 1 and Poly 2 devices, respectively. The DEIS structure is disposed above the poly 1 devices. A silicon nitride (Si.sub.3 N.sub.4) layer is used to mask the DEIS structure and prevents it from oxidizing during certain processing steps. A thin layer of poly x is placed between the DEIS structure and the Si.sub.3 N.sub.4. The poly x layer forms a buffer and protects the DEIS during an etching step which removes the Si.sub.3 N.sub.4 layer.

Process for fabricating semi-conductive oxide between two poly silicon

A method for providing high density multiple level metallurgy for integrated circuit devices in which a relatively thin layer of plasma produced silicon nitride is deposited over a first level of interconnection metallurgy formed on a layer of silicon oxide. Overlap via holes are etched in the nitride layer followed by deposition of a thicker layer of polyimide forming polymer. A second set of via holes larger than the first are provided in the polymer layer and a second layer of interconnection metallurgy is then deposited by a lift-off deposition technique.

Method for forming dense multilevel interconnection metallurgy for

The disclosure teaches the use of aluminum nitride as a mask for utilization of ion implantation in the formation of semiconductor configurations as well as an underlying material for use in semiconductor lift-off techniques in device formation and the deposition of metallization contact lines and interconnections.

Semiconductor masking for device fabrication utilizing ion implantation

Fully integrated non-volatile and fixed threshold field effect devices are fabricated in N-channel technology on a single semiconductor substrate. MOSFET devices of the metal-nitride-oxide-semiconductor (MNOS) devices are used both as fixed threshold support devices and as variable threshold non-volatile memory array devices. Extremely stable and reproducible device characteristics result from the use of low charge containing dielectrics which allow optimum variable threshold stability and allow the use of operating potentials compatable with conventional fixed threshold FET devices. Low temperature processing following deposition of variable threshold gate dielectric enables all enhancement mode operation. A field oxide structure including a thin silicon dioxide layer, an aluminum oxide layer and a nitride layer provides parasitic threshold voltages in excess of 60 volts and prevents sub-threshold leakage.

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Raleigh, NC, United States of America

Charles T Kroll