Sun Microsystems, Inc.

Charles T Cheng

Robert Cypher

Michael W Parkin

John M Lo

A memory controller, system, and methods are disclosed. The system comprises a memory controller interconnected to a plurality of memory chips. Each memory chip stores data at a plurality of locations. The memory controller performs a sparing transaction comprising reading data from a given location of one or more of the memory chips including a first memory chip, writing the data to a given location of one or more of the memory chips including a second memory chip, wherein during writing, data from the first memory chip is written to the second memory chip, and allowing additional memory transactions directed to the memory chips between the start of reading and the end of writing unless the additional memory transaction is targeted to the given location. In a further embodiment, the sparing transaction comprises correcting errors in the data before writing the data.

Data corruption avoidance in DRAM chip sparing

A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or state machine operating in parallel dequeues packets and forwards them (e.g., to an InfiniBand node). Packets are stored in the shared packet memory, and status/control information is stored in a control memory that is updated for each packet enqueue and packet dequeue. Prior to updating the packet and/or control memory, each process interfaces with the other to determine if the other process is active and/or to identify the other process' current communication connection. If the enqueue process detects a collision, it pauses (e.g., for a predetermined number of clock cycles). If the dequeue process detects a collision, it selects a different communication connection to dequeue.

Method and apparatus for avoiding collisions during packet enqueue and dequeue

A method and apparatus are provided for caching data for protocol processing. A protocol processing cache stores data needed for the generation of new headers, from both receive and transmit flows. Some data may be stored in the cache only after being processed (e.g., updated, calculated) by a protocol processor. Other data may bypass the protocol processor and be stored in the cache without being handled by the protocol processor. An entry in the cache includes data needed for header generation, a tag identifying an index into a control block memory of the TCP connection to which the data corresponds. An entry may also include one or more control indicators to indicate whether a transmit flow has been acknowledged, whether a receive flow has been observed, and whether the transmit flow has been updated with control data from the receive flow. The apparatus is protocol processor independent.

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Milpitas, CA, United States of America

Charles T Cheng