Digital Equipment Corporation

Encore Computer Corporation

Charles S Namias

David J Schanin

Thomas Courtenay Porcher

John W Eng

Russel L Moore

John Reed Bartlett

Steven J Frank

David B Hughes

Stephen S Corbin

Robert S DiNitto

Trevor A Creary

David W Zopf

Mark J Matale

Brian D Gill

David F Ford

Disclosed is a multiprocessor computer system including a plurality of processor modules with each of the processor modules including at least one processor and a cache memory which is shared by all of the processors of each processor module. The processor modules are connected to a system bus which comprises independent data, address, vectored interrupt, and control buses. A system memory which is shared by all the processor modules is also connected to the buses, and the cache memories in each processor module store those memory locations in the main memory most frequently accessed by the processors in its module. A system control module controls the operation and interaction of all of the modules and contains the bus arbiters for the vector, data and address buses. The system control module also controls the retrying of requests which are not completed and should any requester fail to obtain access to a bus, the system control module also unjams this deadlock. Each of these multiprocessor computer systems can be connected to another multiprocessor computer system through an interface which includes a cache for housing frequently accessed locations of the other multiprocessor system.

Multiprocessor computer system employing a plurality of tightly coupled

The present invention includes a microprocessor which acts to generate groups of its signals from its read only memory (ROM) thereby forming character representations of groups of coded signals, such as ASCII coded signals, coming from a main data processing device. The groups of bit signals are temporarily stored in a buffer which at a subsequent time transmits, in parallel, groups of said bit signals to a bit map memory through some logic circuitry. The group, or block, transfer of said bit signals in parallel, occurs during horizontal or vertical blank periods. The parallel transfer during the blank periods provides part of the basis for acceleration of the data to a display device as compared with the prior art. In addition, the microprocessor provides address information signals to a graphic display controller, which in turn provides starting addresses, for the locations of the bit signals. In addition a bit map memory device is employed to provide pixel information to a CRT display device to create the characters which are to be shown.

Arrangement for providing data signals for a data display system

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Burlington, MA, United States of America

Charles S Namias