Sandisk Technologies Inc.

Micron Technology Incorporated

Sandisk Enterprise IP LLC

Charles S Kwong

Yingda Dong

Jiahui Yuan

Liang Pang

Tingjun Xie

Hong-Yan Chen

Zhengang Chen

Zhenlei Shen

Sai Krishna Mylavarapu

Jian Feng Chen

Zhenming Zhou

Jiangli Zhu

Seungjune Jeon

Wei Zhao

Pao-Ling Koh

A processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units; responsive to performing each write operation on a respective first memory unit of the memory device, the processing device is configured to identify a candidate memory unit that has been written to by a at least a threshold fraction of the plurality of write operations performed on the memory device; determine whether a threshold refresh criterion is satisfied; and responsive to determining that the threshold refresh criterion is satisfied, refresh data stored at one or more of the memory units that are proximate to the candidate memory unit.

Managing write disturb based on identification of frequently-written memory units

Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.

Defect detection in memories with time-varying bit error rate

Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).

Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. Countermeasures are provided for a first read situation in which a memory is read after a power on event or after a long delay since a last read. Read voltages of lower or higher programmed data states are set according to a positive or negative temperature coefficient (Tco), respectively. Read voltages for error recovery can be set similarly. In another aspect, a wait period between a dummy voltage and a read voltage is a function of temperature. In another aspect, word line voltages of unselected blocks are set according to a negative Tco. In another aspect, pass voltages are set based on a Tco for each programmed data state.

Dynamic tuning of first read countermeasures

Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. In one aspect, a dummy voltage is applied to the word lines to cause a coupling up of the word lines and weak programming. This can occur when a specified amount of time has elapsed since a last program or read operation, or when a power on event is detected for the memory device. A number of read errors can also be considered. The dummy voltage is similar to a pass voltage of a program or read operation but no sensing is performed. The word line voltages are therefore provided at a consistently up-coupled level so that read operations are consistent. The coupling up occurs due to capacitive coupling between the word line and the channel.

Dummy voltage to reduce first read effect in memory

Read disturb is reduced in a charge-trapping memory device such as a 3D memory device by optimizing the channel boosting voltage in an unselected NAND string. A pass voltage applied to the unselected word lines can cause a large gradient in the channel which leads to electron-hole formation and a hot electron injection (HEI) type of read disturb. When the selected word line is close to the source-side of the NAND string, HEI disturb occurs on the drain-side of the selected word line. To avoid this disturb, a spike is provided in the control gate voltage of a drain-side selected gate transistor to temporarily connect the channel to the bit line, lowering the voltage of the associated channel region. A similar approach is used for a drain-side selected word line. The spike may be omitted when the selected word line is mid-range.

Method of reducing hot electron injection type of read disturb in memory

Techniques for detecting word line layers which are shorted together due to a defect in a three-dimensional stack memory device, and for recovering data. The memory device comprises blocks of memory cells in which each block has a separate stack of word line layers but the word line layers at a common height in the different stacks are connected. A process to detect a short circuit occurs when an nth word line layer (WLn) in an ith block fails to successfully complete programming. A determination is made as to whether WLn is shorted to WLn&#x2212;1 and/or WLn+1. If WLn is shorted to WLn+1 but not WLn&#x2212;1 in the ith block, a recovery read process is performed to read the data which has been programmed into the memory cells of WLn of the previously-programmed blocks. The recovery read process uses upshifted control gate read voltages due to the short circuit.

Data recovery in a 3D memory device with a short circuit between word lines

A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an adjacent, previously-programmed memory cell on a common charge-trapping layer. A programming operation avoids program disturb of the programmed data states by using asymmetric pass voltages. Before reading the memory cells on a selected word line (WLn), the memory cells on the adjacent, previously-programmed word line (WLn&#x2212;1) are read. The read operation for WLn uses multiple read voltages&#x2014;one for each data state on WLn&#x2212;1, and one of the read results is selected based on the data state of the adjacent memory cell. Other read operations distinguish between each pair of adjacent programmed data states using a read voltage which is independent of the data state of the adjacent memory cell.

Read with look-back combined with programming with asymmetric boosting in memory

Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, the magnitude of a selected word line voltage is increased to be equal to pass voltages of unselected word lines, and the selected and unselected word line are ramped down at the same time, to avoid creating a channel gradient. In an example verify operation, the above procedure can be followed when the selected word line is at a source-side or middle range among all word lines. When the selected word line is at a drain-side among all word lines, a source-side select gate can be ramped down before the selected word line and a drain-side select gate can be ramped down after the selected word line.

Reducing hot electron injection type of read disturb in 3D non-volatile memory

A NAND string includes dummy memory cells between data memory cells and source-side and drain-side select gates. A gradual increase in threshold voltage (Vth) for the dummy memory cells which occurs due to program-erase cycles is periodically detected by a read operation at an upper checkpoint voltage. If the Vth has increased beyond the checkpoint, the control gate voltage of the dummy memory cells is decreased during subsequent erase operations of program-erase cycles, causing a gradual weak erase. A decrease in the Vth is later detected by a read operation at a lower checkpoint voltage. If the Vth has decreased too much, the control gate voltage is raised during subsequent erase operations, causing a gradual weak programming. The process can be repeated to keep the Vth within a desired range and avoid disturbs due to an increase in a channel voltage gradient which would otherwise occur.

Weak erase of a dummy memory cell to counteract inadvertent programming

The reliability with which data can be read from a storage medium, such as flash memory storage medium, is enhanced by updating an upper limit of a reading threshold voltage window for a respective portion of the storage medium. For each memory cell in the respective portion of the storage medium, a memory controller is configured to perform a plurality of sensing operations and obtain results from the plurality of sensing operations, where the plurality of sensing operations includes sensing operations using a predefined range of offsets from a previously established reading threshold voltage. The memory controller is further configured to determine the updated upper limit of the reading threshold voltage window based on the-results from the plurality of sensing operations, and store the updated upper limit of the reading threshold voltage window for the respective portion of the storage medium.

Device and method for resolving an LM flag issue

A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage.

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Redwood, CA, United States of America

Charles S Kwong