Infineon Technologies Ag

Charles Rimbert-Riviere

Mark Pavier

Angela Kessler

Michael Sielaff

Wolfram Hable

Anton Pugatschow

Marco Sobkowiak

Martin Haller

Ulrich Wilke

Sven Sebastian Buchholz

Michael Daginnus-Metzen

Martin Goldammer

Lydia Lottspeich

Jean-Laurent Deborde

Arne Eilers

Nils Alexander Sanetra

Evelin Palko

Vasile Vartolomei

Benedikt Reuber

A method of producing a power semiconductor module includes providing a power electronics carrier that includes a structured metallization layer disposed on an electrically insulating substrate layer, performing a production step of the power semiconductor module using the power electronics carrier, using a sensor to obtain crack information during the production step, the crack information comprising information about whether one or more cracks occurred in the electrically insulating substrate layer during the production step, analyzing the crack information, and performing one or more of the following after analyzing the crack information: performing a subsequent production step of the power semiconductor module dependent upon the analyzed crack information, cataloging the analyzed crack information, and performing a further investigative step to inspect the electrically insulating substrate layer using the analyzed crack information.

Semiconductor power module with crack sensing

A method includes forming a plurality of perforations in a ceramic mastercard by a first laser process, wherein forming the plurality of perforations includes reducing a first thickness of the ceramic mastercard to a second thickness along first predefined lines, and cutting through an entire thickness of the ceramic mastercard along a plurality of second predefined lines by a second laser process, wherein the first predefined lines and the second predefined lines overlap only partly.

Method for separating substrates

A method for forming a semiconductor substrate arrangement includes: forming a mask on a semiconductor substrate, the semiconductor substrate including and a metallization layer arranged on an insulation layer, the metallization layer arranged between the mask and insulation layer; forming a layer of electrically conductive coating on the metallization layer, the electrically conductive coating formed in at least one opening of the mask on regions of the metallization layer that are not covered by the mask; and after forming the electrically conductive coating, removing the mask. Forming the mask includes either applying an even layer of material on the metallization layer, or applying the material of the mask on the metallization layer such that the thickness of the mask in a region adjacent to edges of the mask is greater than the thickness of the regions of the mask further away from the edges.

Method for forming a semiconductor substrate arrangement

A transportation system for semiconductor substrates includes a tray, lid and packaging bag. The tray includes a bottom and circumferential sidewalls. The tray has an opening on a top side and is configured to receive semiconductor substrates through the opening, the substrates being stacked onto each other in the tray in parallel to the tray bottom. The lid includes a cover plate and at least two arms extending from the plate. The arms are configured to be inserted into the tray between the tray sidewalls and the semiconductor substrates. The cover plate is configured to cover the tray opening when the lid is fully mounted to the tray. The packaging bag is configured to enclose the tray with the substrates stacked therein and lid arranged thereon, and to be evacuated of air and sealed such that the tray and lid arranged in the bag are vacuum sealed inside the bag.

Transport system

A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.

Molded package with chip carrier comprising brazed electrically conductive layers

A method for soldering an insulating substrate onto a substrate mounting portion of a carrier by a predefined solder is provided. The insulating substrate includes a dielectric insulation carrier, a top side, and a bottom side opposite to the top side. The method includes selecting the insulating substrate based on a criterion which indicates that the insulating substrate, if it has the solidus temperature of the solder, has a positive unevenness. The insulating substrate is soldered on the bottom side to the substrate mounting portion, such that, after the soldering, the solidified solder extends continuously from the bottom side of the insulating substrate as far as the substrate mounting portion. The top side of the insulating substrate is populated with at least one semiconductor chip.

Selecting a substrate to be soldered to a carrier

A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.

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Soest, Germany

Charles Rimbert-Riviere