3com Corporation

Charles R Weaver

Gary D Lorenz

Brian J Myrick

Bruce W Thompson

A switching architecture for very high data rates which is placed between a port connecting to a fiber optic gigabit ethernet link and a two Gbit/sec backplane of a concentrator. A port connects to the link for both receiving and transmitting data packets from and to the link. A first FTE receives a data packet from the port, and analyzes the data packet to determine if the data packet should be forwarded to the backplane of the concentrator. If the data packet is to be forwarded, the first FTE sends the data packet to a backplane connection for connecting to the backplane of the network concentrator. A second FTE is connected to the backplane connection. The second FTE receives a data packet from the backplane connection, and analyzes the data packet in a manner similar to the first FTE to determine if a packet should be forwarded to the port. The process of the second FTE with regard to the data packets is substantially similar to the process of the first FTE, except that it is determined whether or not the data packets from the backplane should be forwarded to the port. This switch architecture therefore uses separate transmit and receive channels with independent forwarding tables. The first and second FTE's can be substantially identical, and are preferably switch engine ASIC's (Application Specific Integrated Circuit) designed for a lower data rate.

High speed switch architecture using separate transmit and receive channels with independent forwarding tables

A plural interface LAN switch arbitration method dividing access to a packet memory into a plurality of sequential cycles. A refresher is provided for refreshing the packet memory and the refresher issues a refresher request when the refresher needs to access the packet memory. A first and second interface are provided for transferring data between the packet memory and the respective first and second LAN's. The first and second interface issue a respective first and second interface request when the respective interface needs to access the packet memory. A processor is provided for updating the packet memory and issues a processor request when the processor needs to access the packet memory. The arbitration provides the refresher with an immediately next cycle of the memory when the refresher request is present. The arbitration method also provides the processor with an immediately next cycle of the packet memory when the processor request is present and the refresher has a present cycle which guarantees the processor periodic access to the memory.

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Leominster, MA, United States of America

Charles R Weaver