Vlsi Technology, Inc.

Charles R Rimpo

William K Hilton

Franklyn H Story

Walter H Potts

Gregg D Lahti

Joe A Thomsen

Mitch A Stones

A multi-purpose keyboard controller includes a matrix keyboard control circuit, a serial keyboard control circuit, a PC/AT port control circuit, and an external interface for RTC control. These control circuits are coupled in parallel with the interface logic of the computer system and use the built-in SMI interrupt mechanism of the computer system for reading and writing the keyboard or capturing keypress events. Software BIOS setup is employed to select one of the keyboard control circuits for utilization with the particular personal computer with which the system is employed. The interrupt scheme used by the keyboard interface uses SMI interrupts to the processor and SMI based software routines to read and write the values to and from the keyboard, thereby eliminating the need for dedicating a special hardware interrupt level; so that the system remains compatible with the DOS PC/AT Port 60/64h software interface.

Multi-purposes keyboard interface

A software programmable memory addressing system operates with multiple banks of DRAM chips. The DRAM chips in the different banks may be of different sizes and may be located physically in arrangements where the largest memory chips are not necessarily placed in the first memory bank. The system permits 256K, 1M, and 4M DRAMs to be supported separately, and in combinations of any two of the three types. An internal DRAM controller generates row address strobes (RAS) and column address strobes (CAS) which are supplied to a multiplexer switch bank for routing the RAS and CAS strobes to the physical DRAM banks according to a program set in a register used to control the operation of the multiplexers. Consequently, internally generated logical RAS and CAS signals are routed to the appropriate physical banks of DRAM to create a valid memory map, without requiring the physical arrangement of the banks of DRAMs in a pre-established order.

Programmable memory addressing

Apparatus for providing a boundary between on-board CPU memory and slot bus (EMS) memory is disclosed. A programmable comparator compares the CPU address with a pre-determined address in order to permit the memory array to be accessed by the CPU address or the EMS register, thus preventing the same memory array from being accessed by both the CPU address and the EMS register.

Programmable boundary between system board memory and slot bus memory

A hardware system provides a programmable method for addressing expanded memory specification (EMS) registers in a personal computing system functioning with an MS-Dos.RTM. operating system or the like. The system provides hardware flexibility for addressing EMS registers at different addresses than the standard LIM EMS specification calls for, to permit utilization of register addresses in otherwise unavailable locations. The address translations are effected through hardware; so that no additional delays in the circuit operation occur.

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Mesa, AZ, United States of America

Charles R Rimpo